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Patent # Description
US-8,200,884 Reconfigurable memory module and method
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided...
US-8,200,768 Deferred reading of email database in mobile environments
Systems, methods, computer program product embodiments for deferred reading of email databases are described herein. An embodiment includes an event listener...
US-8,200,031 Multisampling with reduced bit samples
A relatively non-complex signal processor supporting an active pixel sensor imaging system is disclosed. The signal processor only requires the first sample...
US-8,199,599 Variable memory refresh devices and methods
Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples...
US-8,199,595 Techniques for sensing a semiconductor memory device
Techniques for sensing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus...
US-8,199,585 Dynamic soft program trims
Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming...
US-8,199,574 Apparatus comparing verified data to original data in the programming of a memory array
Apparatus configured to perform a programming operation on at least one memory cell of the memory array in response to original data, and further configured to...
US-8,199,572 Non-volatile memory with both single and multiple level cells
Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled...
US-8,199,566 Write performance of phase change memory using set-pulse shaping
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-8,199,556 Methods of reading and using memory cells
Some embodiments include methods of reading memory cells. The memory cells have a write operation that occurs only if a voltage of sufficient absolute value is...
US-8,199,432 Extended tape path length between nip point and guide in tape drive
One embodiment is a method that extends a tape path to compensate for misalignment between tape on a reel and a head by exiting the tape twice from a tape pack...
US-8,199,033 Haptic keyboard systems and methods
Various embodiments provide keyboards that utilize electrically-deformable material as an actuating mechanism to provide haptic feedback to a user of the...
US-8,198,910 Transmitter apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to drive an output with a data signal and to boost a potential of the output in response to a boost...
US-8,198,720 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
US-8,198,717 Signal shifting to allow independent control of identical stacked memory modules
A memory device having die-stacking modules that are interchangeable within a Package-on-Package (PoP) and provide separate Chip Enable (CE) signals for all...
US-8,198,172 Methods of forming integrated circuits using donor and acceptor substrates
Methods for fabricating integrated circuit devices on an acceptor substrate devoid of circuitry are disclosed. Integrated circuit devices are formed by...
US-8,198,160 Vertical transistor phase change memory
Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on...
US-8,198,138 Methods for providing and using grid array packages
Methods for providing and using semiconductor device assemblies or packages include providing or using various elements of a semiconductor device assembly or...
US-8,198,129 Methods of depositing antimony-comprising phase change material onto a substrate and methods of forming phase...
A method of depositing an antimony-comprising phase change material onto a substrate includes providing a reducing agent and vaporized Sb(OR).sub.3 to a...
US-8,198,124 Methods of self-aligned growth of chalcogenide memory access device
Self-aligning fabrication methods for forming memory access devices comprising a doped chalcogenide material. The methods may be used for forming...
US-8,197,622 System and method for detecting features on a laminated veneer lumber billet
The disclosure relates to systems and methods for detecting features on billets of laminated veneer lumber (LVL). In some embodiments, an LVL billet is provided...
US-8,197,115 Luminaire with adjustable light source
Light sources in a luminaire attach to the luminaire by one or more tabs. Up to three axis of rotation are possible. Bendable tabs enable a first axis of...
US-8,196,327 Modular magazine assembly
A modular magazine for a firearm is disclosed. The magazine has a tower and a magazine body. The tower and magazine body are modular and can be disconnected...
US-D661,711 Gripping attachment for backhoe or excavator
US-D661,567 Telescoping wand with double nozzle
US-8,195,920 Active memory command engine and method
A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or...
US-8,195,899 Memory cell operation
The present disclosure includes memory devices and systems having memory cells, as well as methods for operating the memory cells. One or more methods for...
US-8,195,020 Resonator for thermo optic device
A resonator for thermo optic devices is formed in the same process steps as a waveguide and is formed in a depression of a lower cladding while the waveguide is...
US-8,194,487 Refreshing data of memory cells with electrically floating body transistors
A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one...
US-8,194,477 Subtraction circuits and digital-to-analog converters for semiconductor devices
A memory device that, in certain embodiments, includes a plurality of memory elements connected to a bit-line and a delta-sigma modulator with a digital output...
US-8,194,475 Capacitive divider sensing of memory cells
The present disclosure includes devices and methods for sensing resistance variable memory cells. One device embodiment includes at least one resistance...
US-8,194,474 Data bus power-reduced semiconductor storage apparatus
In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a...
US-8,194,466 Charge pump operation in a non-volatile memory device
A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial...
US-8,194,460 Charge loss compensation during programming of a memory device
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a...
US-8,194,459 Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal...
US-8,194,458 Programming and/or erasing a memory device in response to its program and/or erase history
For one embodiment, a program starting voltage of one or more program pulses applied to one or more memory cells is in response, at least in part, to on a...
US-8,194,454 Interleaved memory program and verify method, device and system
An interleaved memory programming and verification method, device and system includes a memory array including first and second memory banks of memory cells....
US-8,194,450 Methods and control circuitry for programming memory cells
Methods of programming memory cells and control circuitry for memory arrays facilitate a reduction of program disturb. A memory cell is shifted from a first...
US-8,194,446 Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply...
Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less...
US-8,194,441 Phase change memory state determination using threshold edge detection
Subject matter disclosed herein relates to techniques to read a memory cell that involve a threshold edge phenomenon of a reset state of phase change memory.
US-8,194,433 Method and apparatus for accessing a bidirectional memory
A bidirectional memory cell includes an ovonic threshold switch (OTS) and a bidirectional memory element. The OTS is configured to select the bidirectional...
US-8,194,282 Image forming apparatus for identifying undesirable toner placement
A method and apparatus for printing data on a print medium is disclosed. The apparatus is configured to format print data to pixel data, the pixel data...
US-8,194,257 Simplified operation of scan based devices
A document scanner comprises a scan bed, and a processor means which is adapted to: analyse a scanned image to detect one or more defined markings on the...
US-8,193,849 Generating a full rail signal
Apparatus, systems, and methods are disclosed, such as those that comprise a center-swing signal generator that includes a push-pull center-swing driver coupled...
US-8,193,646 Semiconductor component having through wire interconnect (TWI) with compressed wire
A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact....
US-8,193,607 Memory cell having GeN-containing material and variable resistance material embedded within insulating material
A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the...
US-8,193,602 Schottky diode with control gate for optimization of the on state resistance, the reverse leakage, and the...
A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated...
US-8,193,590 Interconnecting bit lines in memory devices for multiplexing
An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second...
US-8,193,568 Nanocrystal based universal memory cells, and memory cells
Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element...
US-8,193,521 Resistive memory cell fabrication methods and devices
A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom...
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