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Patent # Description
US-8,124,541 Etchant gas and a method for removing material from a late transition metal structure
An etchant gas and a method for removing at least a portion of a late transition metal structure. The etchant gas includes PF.sub.3 and at least one oxidizing...
US-8,124,528 Method for forming a ruthenium film
Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.
US-8,124,522 Reducing UV and dielectric diffusion barrier interaction through the modulation of optical properties
Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric...
US-8,124,491 Container capacitor structure and method of formation thereof
Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of...
US-8,124,456 Methods for securing semiconductor devices using elongated fasteners
Semiconductor device assemblies include elements such as electronic components and substrates secured together by a fastener that includes an elongated portion...
US-8,124,445 Confined resistance variable memory cell structures and methods
Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell...
US-8,124,414 Taggants, method for forming a taggant, and a method for detecting an object
A taggant comprising at least one perfluorocarbon compound surrounded by a polyphosphazene compound. The polyphosphazene compound has the chemical structure: ...
US-8,124,389 Crystal structure of aldehyde dehydrogenase and methods of use thereof
The present disclosure provides a crystal structure of aldehyde dehydrogenase (ALDH) with a modulator of ALDH bound thereto. The present disclosure provides a...
US-8,124,326 Methods of patterning positive photoresist
A method of patterning positive photoresist includes providing positive photoresist over a substrate. An area of the positive photoresist is exposed to a...
US-8,124,320 Method and apparatus for surface tension control in advanced photolithography
A method and apparatus are used for cleaning and drying a semiconductor wafer. Within a sealable chamber, a wafer having photoresist features thereon is spun...
US-8,123,968 Multiple deposition for integration of spacers in pitch multiplication process
Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the...
US-8,123,962 Alternating self-assembling morphologies of diblock copolymers controlled by variations in surfaces
Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block...
US-8,123,961 Extensions of self-assembled structures to increased dimensions via a "bootstrap" self-templating method
Methods for fabricating sublithographic, nanoscale arrays of openings and linear microchannels utilizing self-assembling block copolymers, and films and devices...
US-8,123,960 Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers
Methods for fabricating sublithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming...
US-8,122,780 Explosion proof vehicle for tank inspection
An Explosion Proof Vehicle (EPV) having an interior substantially filled with an inert fluid creating an interior pressure greater than the exterior pressure....
US-8,122,635 Shotgun forearm-stock shot shell carrier
A shotgun forearm-stock shot shell carrier, for storing multiples of shotgun shells and quickly releasing the same for hand loading into a shotgun magazine or...
US-8,122,632 Dynamic magazine latch
A dynamic latch to selectively retain a magazine within the magazine port of a long gun. The dynamic latch permits the magazine to be inserted into the magazine...
US-D655,048 Helmet
US-D654,700 Brush head
US-8,122,447 Firmware installation
A firmware bundle is download to a non-operational storage area without changing a live copy of firmware in a device. The firmware bundle is downloaded in order...
US-8,122,321 Methods of data handling
Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the...
US-8,122,304 JTAG controlled self-repair after packaging
An integrated circuit containing memory includes IEEE 1149.1 (JTAG) controlled self-repair system that permits permanent repair of the memory after the...
US-8,122,220 Memory usage in imaging devices
Imaging devices incorporating semi-volatile memory are described herein. According to various embodiments, a communication interface may receive image data that...
US-8,121,436 Methods and systems for image scaling
Methods and systems for scaling an input image are provided. A pixel neighborhood that includes a plurality of pixels neighboring a pixel is selected. At least...
US-8,121,337 Free air magnetic circuit and speaker
Disclosed is a free air magnetic circuit and speaker in which no pole piece is used. A magnet layer is located between a top plate and a back plate with a gap...
US-8,121,018 Signal transmitting method, signal receiving method and signal receiving device in OFDM system
A signal transmitting method, a signal receiving method, and a signal receiving device are adapted to an OFDM system. In the signal transmitting method and...
US-8,120,969 Semi-volatile NAND flash memory
Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash...
US-8,120,954 Method, apparatus, and system for erasing memory
Methods, apparatus, and systems may operate to perform a pre-programming operation on a plurality of multiple level memory cells of a memory device. An example...
US-8,120,952 Memory device with a decreasing dynamic pass voltage for reducing read-disturb effect
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to...
US-8,120,951 Memory devices, memory device constructions, constructions, memory device forming methods, current conducting...
Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive...
US-8,120,943 Accessing a phase change memory
A memory employs a low-level current source to access a phase change memory cell. The current source charges an access capacitor in order to store sufficient...
US-8,120,876 Medium for use in a tape drive apparatus having identification segment and a segment identification pattern
A tape medium has an identification segment located on a transparent leader segment of the tape medium for optical detection of the segment identification...
US-8,120,696 Methods, apparatuses and systems using windowing to accelerate automatic camera functions
Methods, apparatuses and systems are disclosed for accelerating the operation of the automatic functions of an imager, e.g. a camera system. The automatic...
US-8,120,632 Allignment of color planes in multi-beam multi-pass printers
Methods and apparatuses that facilitate the alignment of multiple color planes of a latent image in a multi-beam multi-pass printer are described herein. The...
US-8,120,521 Radar echolocater with audio output
The echolocater device described herein incorporates the features of integrated sampling radar technology to create a unique device that provides, for example,...
US-8,120,184 Semiconductor constructions and methods of forming layers
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
US-8,120,167 System with semiconductor components having encapsulated through wire interconnects (TWI)
A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first...
US-8,120,137 Isolation trench structure
Among structures, methods, devices, and systems for isolation trenches, a semiconductor device is provided that includes a substrate and an isolation trench...
US-8,120,134 High-performance diode device structure and materials used for the same
A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has...
US-8,120,124 Ultra thin TCS (SiCl.sub.4) cell nitride for DRAM capacitor with DCS (SiH.sub.2Cl.sub.2) interface seeding layer
A method for forming silicon nitride films on semiconductor devices is provided. In one embodiment of the method, a silicon-comprising substrate is first...
US-8,120,109 Low dose super deep source/drain implant
A semiconductor device for reducing junction capacitance by an additional low dose super deep source/drain implant and a method for its fabrication are...
US-8,120,101 Semiconductor constructions and transistors, and methods of forming semiconductor constructions and transistors
The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the...
US-8,120,083 Polymer-based ferroelectric memory
Apparatus and systems may comprise electrode structures that include two or more dissimilar and abutting metal layers on a surface, some of the electrode...
US-8,120,072 JFET devices with increased barrier height and methods of making same
Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present...
US-8,119,543 Methods of reducing defect formation on silicon dioxide formed by atomic layer deposition (ALD) processes
Methods for reducing and inhibiting defect formation on silicon dioxide formed by atomic layer deposition (ALD) are disclosed. Defect reduction is accomplished...
US-8,119,537 Selective etching of oxides to metal nitrides and metal oxides
A method is provided for selectively etching native oxides or other contaminants to metal nitrides and metal oxides during manufacture of a semiconductor...
US-8,119,535 Pitch reduced patterns relative to photolithography features
Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns....
US-8,119,514 Cobalt-doped indium-tin oxide films and methods
Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism....
US-8,119,484 DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
US-8,119,483 Methods of forming memory cells
Some embodiments include methods of utilizing polysilazane in forming non-volatile memory cells. The memory cells may be multi-level cells (MLCs). The...
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