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Patent # Description
US-7,995,395 Charge loss compensation during programming of a memory device
A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a...
US-7,995,391 Multiple select gates with non-volatile memory cells
Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and...
US-7,995,371 Threshold device for a memory array
A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different...
US-7,995,365 Method and apparatuses for managing double data rate in non-volatile memory
Described herein are a method and apparatuses for providing DDR memory access. In one embodiment, an apparatus includes a data storage unit to store and...
US-7,995,244 Halftoner block employing average values and shifts
Halftoning apparatus and method that may generate and employ average values and shifts are described herein. The apparatus may include an unpacker to determine...
US-7,994,922 Communications system and method with A/D converter
A communications system includes a radio frequency identification device including an integrated circuit having a single die including a microprocessor, a...
US-7,994,849 Devices, systems, and methods for generating a reference voltage
Methods, devices, and systems are disclosed for a voltage reference generator. A voltage reference generator may comprise a bandgap voltage reference circuit...
US-7,994,836 Latch with clocked devices
A latch circuit includes a feed-forward circuit, a keeper circuit, and a feed-back circuit. The feed-forward circuit includes a first-inverting-stage with a...
US-7,994,595 Strained semiconductor by full wafer bonding
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined...
US-7,994,566 Stacked non-volatile memory with silicon carbide-based amorphous silicon finFETs
A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a...
US-7,994,547 Semiconductor devices and assemblies including back side redistribution layers in association with through...
Low temperature processed back side redistribution lines (RDLs) are disclosed. Low temperature processed back side RDLs may be electrically connected to the...
US-7,994,491 PCRAM device with switching glass layer
A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and...
US-7,994,464 Dual conversion gain gate and capacitor combination
A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective...
US-7,994,108 Composition useful for removal of post-etch photoresist and bottom anti-reflection coatings
An aqueous-based composition and process for removing hardened photoresist and/or bottom anti-reflective coating (BARC) material from a microelectronic device...
US-7,993,988 Techniques for fabricating a non-planar transistor
Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member)....
US-7,993,977 Method of forming molded standoff structures on integrated circuit devices
A method of forming molding standoff structures on integrated circuit devices is disclosed which includes forming a plurality of standoff structures on a...
US-7,993,957 Phase change memory cell and manufacturing method thereof using minitrenches
A process forms a phase change memory cell using a resistive element and a memory region of a phase change material. The resistive element has a first thin...
US-7,993,944 Microelectronic imagers with optical devices having integral reference features and methods for manufacturing...
Microelectronic imager assemblies with optical devices having integral reference features and methods for assembling such microelectronic imagers is disclosed...
US-7,993,539 Methods of etching nanodots, methods of removing nanodots from substrates, methods of fabricating integrated...
Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated...
US-7,993,413 Valve system for prosthetics
A valve system regulates the air pressure in the space(s) between a residual limb, or liner-covered limb, and a hard socket of an external prosthesis, and may...
US-7,993,093 Systems and methods for wafer translation
A two-axis automation system can be used to transfer and rotate wafers between horizontal and vertical orientations necessary for differing steps in a...
US-7,992,297 Method for forming a circuit board via structure for high speed signaling
One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage...
US-D643,169 Vacuum cleaner floor tool
US-7,992,204 Enhanced responses to online fraud
Solutions (including inter alia, systems, methods and software) for dealing with online fraud. Certain of these solutions provide enhanced responses to an...
US-7,992,201 Dynamic network tunnel endpoint selection
Dynamically selecting an endpoint for a tunnel into an enterprise computing infrastructure. A client dynamically selects a gateway (which may alternatively be...
US-7,992,060 Apparatus, methods, and system of NAND defect management
Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a...
US-7,991,947 Multi-priority encoder
A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder...
US-7,991,571 Providing nonlinear temperature compensation for sensing means by use of pade approximant function emulators
Pade Approximant function emulators are used to model the nonlinear offset and/or nonlinear sensitivity behaviors of a sensor relative to temperature sub-ranges...
US-7,991,281 Illumination source having programmable rise and fall times
An illumination source senses a level of ambient light and determines an illumination waveform to be used to illuminate at least a portion of a document. The...
US-7,991,098 Method and apparatus for training the reference voltage level and data sample timing in a receiver
Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises...
US-7,990,802 Selective edge phase mixing
Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and...
US-7,990,792 Hybrid sense amplifier and method, and memory device using same
Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit....
US-7,990,775 Methods of operating memory devices including different sets of logical erase blocks
Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second...
US-7,990,772 Memory device having improved programming operation
Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and...
US-7,990,763 Memory with weighted multi-page read
A memory device provides increased output data to help evaluate data errors arising from bit line coupling and floating gate coupling during a read operation....
US-7,990,761 Immunity of phase change material to disturb in the amorphous phase
Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset...
US-7,990,446 High dynamic range pixel amplifier
A pixel cell with increased dynamic range is formed by providing a floating diffusion region having a variable capacitance, controlled by at least one gate...
US-7,990,427 Method and apparatus for applying tonal correction to images
A method and apparatus for applying tonal correction to images to obtain a more pleasing photographic image by redistributing low-key, mid-tone and high-key...
US-7,990,412 Systems and methods for correcting image perspective
Systems and methods for correcting perspective in an image are invented and disclosed. One embodiment comprises capturing image data responsive to light...
US-7,990,391 Memory system having multiple address allocation formats and method for use thereof
A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of...
US-7,990,366 Foot-operated input device
A foot operated data input pad has a plurality of foot-operated buttons that may be used to enter data, information, or instructions, including but not limited...
US-7,990,163 Systems and methods for defect testing of externally accessible integrated circuit interconnects
Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads...
US-7,990,110 Circuits and related methods for charging a battery
An aspect of the present invention provides a circuit for generating a voltage that can be used to recharge a battery. The circuit includes an inductive voltage...
US-7,989,957 Self-aligned, integrated circuit contact
Embodiments concern contacts for use in integrated circuits, which have a reduced likelihood of shorting to unrelated portions of an overlying conductive layer...
US-7,989,870 Use of dilute steam ambient for improvement of flash devices
A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer,...
US-7,989,866 DRAM layout with vertical FETS and method of formation
DRAM cell arrays having a cell area of about 4 F.sup.2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The...
US-7,989,864 Methods for enhancing capacitors having roughened features to increase charge-storage capacity
Structures and methods for making a semiconductor structure are discussed. The semiconductor structure includes a rough surface having protrusions formed from...
US-7,989,749 Method and apparatus providing shared pixel architecture
Methods and apparatuses using pixels with shared readout circuits are used to increase pixel fill factor and operation efficiency.
US-7,989,362 Hafnium lanthanide oxynitride films
Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of...
US-7,989,360 Semiconductor processing methods, and methods for forming silicon dioxide
Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate...
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