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Patent # Description
US-8,024,266 Method for secure, closed-loop money transfer via electronic mail
A method of providing for a money transfer over a network by providing a stamp having a face value and a lifespan both indicated on the stamp, the stamp being a...
US-8,023,934 Synchronizing communications and data between mobile devices and servers
A system, method, and computer program product for synchronizing communications, data, application workflow events, and business processes between a mobile...
US-8,023,350 Memory malfunction prediction system and method
A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of...
US-8,023,344 Data retention kill function
Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon...
US-8,023,343 Systems and methods for issuing address and data signals to a memory array
Embodiments of the present invention include circuitry for issuing address and data signals to a memory array using a system clock and a write clock. A locked...
US-8,023,340 Signal transfer apparatus and methods
Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells...
US-8,023,334 Program window adjust for memory cell signal line delay
A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the...
US-8,023,332 Cell deterioration warning apparatus and method
Memory devices and methods adapted to process and generate analog data signals representative of data values of two or more bits of information facilitate...
US-8,023,329 Reducing effects of program disturb in a memory device
A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the...
US-8,023,324 Memory controller self-calibration for removing systemic influence
Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After...
US-8,023,293 On-die anti-resonance structure for integrated circuit
A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to...
US-8,022,729 Signal driver circuit having adjustable output voltage for a high logic level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured...
US-8,022,536 Semiconductor substrate for build-up packages
The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach...
US-8,022,473 Semiconductor device having reduced sub-threshold leakage
A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed...
US-8,022,385 Memory devices with buried lines
A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically...
US-8,022,147 Zwitterionic block copolymers and methods
Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic...
US-8,021,981 Redistribution layers for microfeature workpieces, and associated systems and methods
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system...
US-8,021,940 Methods for fabricating PMOS metal gate structures
Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate...
US-8,021,928 System and method for routing supply voltages or other signals between side-by-side die and a lead frame for...
An integrated circuit or chip includes a first die and a second die positioned on a lead frame of a package including a lead frame, such as a QFP, DIP, PLCC,...
US-8,021,908 Method and apparatus for dark current and blooming suppression in 4T CMOS imager pixel
A method and apparatus for operating an imager pixel that includes the act of applying a relatively small first polarity voltage and a plurality of pulses of a...
US-8,021,897 Methods of fabricating a cross point memory array
Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal...
US-8,021,446 Self-regulating feedstock delivery systems and hydrogen-generating fuel processing assemblies and fuel cell...
Feedstock delivery systems and hydrogen-producing fuel processing assemblies and fuel cell systems containing the same. The feedstock delivery systems include a...
US-8,020,322 Multi-traction effect shoe cleat
A cleat for a shoe has an annular array of different types of angularly spaced traction elements disposed about and depending from a hub periphery. The array...
US-D645,538 Filter block for liquid filtration
US-8,020,035 Expander circuit for a solid state persistent storage device that provides a plurality of interfaces to...
A system includes a solid state persistent storage device, and a plurality of storage controllers to manage access of the solid state persistent storage device....
US-8,019,967 Robust index storage for non-volatile memory
A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile...
US-8,019,932 Block management for mass storage
An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory...
US-8,019,913 Dynamically setting burst length of double data rate memory device by applying signal to at least one external...
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
US-8,019,863 Synchronizing events between mobile devices and servers
A system, method, and computer program product for synchronizing events between a mobile device and a server are described herein. In an embodiment, the method...
US-8,019,693 Systems and methods for utilizing printing device data in a customer service center
Systems and methods are described for collecting data in component memory of a printing device replaceable component and utilizing the data in a customer...
US-8,018,791 Circuit, system and method for controlling read latency
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit...
US-8,018,786 Method for reading semiconductor memories and semiconductor memory
A phase change memory cells including a memory element or a threshold device is read using a read current which does not threshold either the memory element or...
US-8,018,778 Memory read methods, apparatus, and systems
Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to...
US-8,018,770 Program and sense operations in a non-volatile memory device
Methods for programming and sensing in a memory device, a data cache, and a memory device are disclosed. In one such method, all of the bit lines of a memory...
US-8,018,752 Configurable bandwidth memory devices and methods
Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for...
US-8,018,358 Balanced data bus inversion
A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the "balance" of...
US-8,018,261 Clock generator and methods using closed loop duty cycle correction
Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty...
US-8,018,258 Periodic signal synchronization apparatus, systems, and methods
Apparatus, systems, and methods are disclosed that operate to generate a periodic output signal from a periodic input signal, obtain a plurality of samples of a...
US-8,018,069 Through-hole contacts in a semiconductor device
Devices with conductive through-waver vias. In one embodiment, the device is formed by a method comprising providing a layer of semiconducting material, forming...
US-8,018,015 Buried conductor for imagers
A pixel cell having a photo-conversion device at a surface of a substrate and at least one contact area from which charge or a signal is output or received. A...
US-8,017,988 High density stepped, non-planar flash memory
A first plurality of memory cells is in a first plane in a first column of the array. A second plurality of memory cells is in a second plane in the same...
US-8,017,985 Concentric or nested container capacitor structure for integrated circuits
Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made...
US-8,017,982 Imagers with contact plugs extending through the substrates thereof and imager fabrication methods
Methods for fabricating photoimagers, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating image sensing elements, transistors,...
US-8,017,926 Radiation collimator and systems incorporating same
A collimator including a housing having disposed therein a shield element surrounding a converter core in which a photon beam is generated from electrons...
US-8,017,481 Methods of forming nanoscale floating gate
A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first...
US-8,017,475 Process to improve high-performance capacitors in integrated MOS technologies
A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is...
US-8,017,470 Method of forming a structure over a semiconductor substrate
The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the...
US-8,017,453 Method and apparatus for forming an integrated circuit electrode having a reduced contact area
A method and an apparatus for manufacturing a memory cell having a nonvolatile resistive memory element with a limited size active area. The method comprises a...
US-8,017,184 .beta.-diketiminate ligand sources and metal-containing compounds thereof, and systems and methods including same
The present invention provides metal-containing compounds that include at least one .beta.-diketiminate ligand, and methods of making and using the same. In...
US-8,017,173 Dehydrated mash potato product and process
Dehydrated potato pellets are made by preparing an aqueous mixture of dried potato pieces, an emulsifier, and oil, and, optionally, a freshly cooked potato,...
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