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Patent # Description
US-7,989,349 Methods of manufacturing nanotubes having controlled characteristics
A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further,...
US-7,989,345 Methods of forming blind wafer interconnects, and related structures and assemblies
Methods for forming blind wafer interconnects (BWIs) from the back side surface of a substrate structure to the underside of a bond pad on the opposing surface...
US-7,989,340 Methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive...
The invention included to methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive contacts. In one...
US-7,989,336 Methods of forming a plurality of conductive lines in the fabrication of integrated circuitry, methods of...
A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a...
US-7,989,322 Methods of forming transistors
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-7,989,311 Strained semiconductor by full wafer bonding
One aspect of this disclosure relates to a method for forming a wafer with a strained semiconductor. In various embodiments of the method, a predetermined...
US-7,989,307 Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and...
Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography...
US-7,989,290 Methods for forming rhodium-based charge traps and apparatus including rhodium-based charge traps
Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic...
US-7,989,289 Floating gate structures
Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the...
US-7,989,288 Transistor constructions and processing methods
A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second...
US-7,989,285 Method of forming a film containing dysprosium oxide and hafnium oxide using atomic layer deposition
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO.sub.2) doped with dysprosium (Dy) and a method of fabricating such a...
US-7,989,266 Methods for separating individual semiconductor devices from a carrier
A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be...
US-7,989,251 Variable resistance memory device having reduced bottom contact area and method of forming the same
A variable resistance memory element and method of forming the same. The memory element includes a substrate supporting a bottom electrode having a small bottom...
US-7,989,022 Methods of processing substrates, electrostatic carriers for retaining substrates for processing, and...
A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to...
US-7,988,529 Methods and tools for controlling the removal of material from microfeature workpieces
Methods and apparatus for controlling the removal of material from microfeature workpieces in abrasive removal processes. An embodiment of such a method...
US-7,987,547 Cleansing pad
A cleansing pad (10) is made of a web of fibers, forming a substrate (11), where the substrate (11) includes a cleansing agent (12) therein. The cleansing agent...
US-7,987,525 Helmet
A helmet for use by an operator or rider of a motorized vehicle, such as a motorcycle or snowmobile, includes a ventilation system with an air intake subsystem,...
US-D642,705 Pull tab for removing solidified substance
US-7,987,301 DMA controller executing multiple transactions at non-contiguous system locations
A direct memory access controller comprises a plurality of registers defining parameters for multiple direct memory access transactions and transfer control...
US-7,986,578 Low voltage sense amplifier and sensing method
Systems and methods of sensing a data state coupled to a digit line and for coupling a digit line to a sense amplifier. In sensing the data state coupled to the...
US-7,986,576 Digit line equilibration using access devices at the edge of sub-arrays
A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines...
US-7,986,563 NAND flash memory programming
A method of charging a floating gate in a nonvolatile memory cell comprises bringing a substrate channel within the memory cell to a first voltage, bringing a...
US-7,986,555 Method for programming and erasing an NROM cell
A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain...
US-7,986,553 Programming of a solid state memory utilizing analog communication of bit patterns
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-7,986,549 Apparatus and method for refreshing or toggling a phase-change memory cell
An apparatus and a method for refreshing or toggling a phase-change memory cell are described. The apparatus includes a voltage ramp element coupled to the...
US-7,986,363 High dynamic range imager with a rolling shutter
A high dynamic range imager operates pixels utilizing at least a short integration period and a long integration period. The pixel reading circuits of the...
US-7,985,995 Zr-substituted BaTiO.sub.3 films
The use of atomic layer deposition (ALD) to form a zirconium substituted layer of barium titanium oxide (BaTiO.sub.3), produces a reliable ferroelectric...
US-7,985,963 Memory using variable tunnel barrier widths
A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The...
US-7,985,725 Ultra concentrated liquid laundry detergent
This disclosure relates to ultra concentrated liquid laundry detergent (e.g., 3.times.+ ultra concentrated liquid laundry detergent). For example, this...
US-7,985,698 Methods of forming patterned photoresist layers over semiconductor substrates
This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is...
US-7,985,692 Method to reduce charge buildup during high aspect ratio contact etch
A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide...
US-7,985,681 Method for selectively forming symmetrical or asymmetrical features using a symmetrical photomask during...
A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or...
US-7,985,679 Atomic layer deposition methods
An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is...
US-7,985,658 Method of forming substrate for use in imager devices
A method of fabricating a semiconductor substrate structure comprises forming an oxide region in contact with a first semiconductor, e.g. silicon, substrate,...
US-7,985,617 Methods utilizing microwave radiation during formation of semiconductor constructions
Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during...
US-7,984,870 Multi use strap and cord winder
A strap and cord winder is adjustable for different width straps and reconfigurable for cords. The winder includes a handle assembly with a center shaft and an...
US-7,984,578 Shadow box frame and insert
A shadow box is provided that is configured to display art objects wherein the shadow box has two chambers, the front chamber configured to display art objects...
US-7,984,562 Device and method for marking competition rings and other areas on floor surfaces
A template device is used layout and marking geometric shapes such as martial arts or other sports rings on a floor. The device includes a central body at or...
US-D642,212 Printer
US-7,984,207 Dynamically setting burst length of double data rate memory device by applying signal to at least one external...
One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.
US-7,983,873 Non-contact deviation measurement system
A non-contacting deviation measurement system projects a first line and a second line upon a surface of an object. The projections of the first line and second...
US-7,983,516 Zinc oxide diodes for optical interconnections
The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined...
US-7,983,110 Circuit and method for controlling a clock synchronizing circuit for low power refresh operation
A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a...
US-7,983,108 Row mask addressing
Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional...
US-7,983,104 Page mode access for non-volatile memory arrays
An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory...
US-7,983,090 Memory voltage cycle adjustment
The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes...
US-7,983,088 Programming in a memory device
Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is...
US-7,983,085 Memory array with inverted data-line pairs
At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory...
US-7,983,070 DRAM tunneling access transistor
In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side...
US-7,982,662 Scanning array for obstacle detection and collision avoidance
This scanning array scans an area around the array for nearby objects, collision obstructions, and terrain topography. The scanning array can scan for sounds...
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