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Patent # Description
US-8,111,570 Devices and methods for a threshold voltage difference compensated sense amplifier
Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair...
US-8,111,555 NAND step voltage switching method
Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a...
US-8,111,534 Rank select using a global select pin
Methods, memory devices, and systems are disclosed, such as those for accessing a memory circuit through the use of reduced external pins. With one such system,...
US-8,111,515 Methods and apparatuses for transferring heat from stacked microfeature devices
Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly...
US-8,110,891 Method of increasing deposition rate of silicon dioxide on a catalyst
Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The...
US-8,110,884 Methods of packaging imager devices and optics modules, and resulting assemblies
A method of packaging imager devices and optics modules is disclosed which includes positioning an imager device and an optics module in each of a plurality of...
US-8,110,488 Method for increasing etch rate during deep silicon dry etch
A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of...
US-8,110,469 Graded dielectric layers
Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of...
US-8,110,115 Mobile water treatment
A mobile water treatment apparatus to on-load a dirty fluid into a storage container attached to a motor vehicle and transport the fluid in the storage...
US-8,110,106 Anaerobic digester design and operation
An apparatus for the anaerobic digestion of solid waste is disclosed. The apparatus includes a pre-digestion treatment chamber and an anaerobic digester chamber...
US-8,109,917 Twistable medication dispensing system
Disclosed is a dispenser having a first chamber containing a first fluid and a second chamber containing a second material. Each chamber has screw threads that...
US-D653,698 Eyeglass frame
US-D653,697 Eyeglass
US-8,107,849 Image forming apparatus
A compact image forming apparatus is provided in which stains on the back of a transfer material can be prevented. In particular, in a marginless print mode in...
US-8,107,580 Method and apparatus for generating a phase dependent control signal
A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector...
US-8,107,344 Phase masks for use in holographic data storage
A spatial light modulator (SLM) having a phase mask that is provided as an internal component thereof. The phase mask can be provided as a multilevel surface of...
US-8,107,305 Integrated circuit memory operation apparatus and methods
Some embodiments include apparatus and methods having a memory cell included in a device, a control line configured to receive a control signal to access the...
US-8,107,304 Distributed write data drivers for burst access memories
An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only...
US-8,107,296 Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device
In one of the disclosed embodiments, a write algorithm is used to remove errors due to back pattern effects, cell-to-cell capacitive coupling, and program...
US-8,107,218 Capacitors
Some embodiments include methods of forming capacitors. A metal oxide mixture may be formed over a first capacitor electrode. The metal oxide mixture may have a...
US-8,106,797 Assigning codes to and repairing Huffman trees
A method for assigning codes to Huffman trees and repairing invalid Huffman trees is disclosed using a calculated delta and moving nodes within the Huffman tree...
US-8,106,644 Reference circuit with start-up control, generator, device, system and method including same
A reference generator circuit generates a reference signal for use by a regulator in generating operational power for circuits and devices. A start-up circuit...
US-8,106,520 Signal delivery in stacked device
Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a...
US-8,106,491 Methods of forming stacked semiconductor devices with a leadframe and associated assemblies
A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged...
US-8,106,488 Wafer level packaging
Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of...
US-8,106,438 Stud capacitor device and fabrication method
The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in...
US-8,105,956 Methods of forming silicon oxides and methods of forming interlevel dielectrics
A method of forming silicon oxide includes depositing a silicon nitride-comprising material over a substrate. The silicon nitride-comprising material has an...
US-8,105,896 Methods of forming capacitors
A method of forming a capacitor includes forming a conductive first capacitor electrode material comprising TiN over a substrate. TiN of the TiN-comprising...
US-8,105,864 Method of forming barrier regions for image sensors
Embodiments of the invention provide an image sensor that includes a barrier region for isolating devices. The image sensor comprises a substrate and an array...
US-8,105,862 Imager with tuned color filter
An optimized color filter array is formed in, above or below one or more damascene layers. The color filter array includes filter regions which are configured...
US-8,105,858 CMOS imager having a nitride dielectric
An imaging device formed as a CMOS semiconductor integrated circuit includes a nitrogen containing insulating material beneath a photogate. The nitrogen...
US-8,105,131 Method and apparatus for removing material from microfeature workpieces
Methods and apparatus for removing materials from microfeature workpieces. One embodiment of a subpad in accordance with the invention comprises a matrix having...
US-8,104,217 Riflescope high speed adjusting elevation assembly
A riflescope high speed, coarse and fine adjustment assembly that includes a riflescope with an erector tube located inside a scope body. Formed on the scope...
US-8,104,209 Dynamic latch for a tube mounted magazine well
A dynamic latch to selectively retain a magazine within the magazine port of a long gun. The dynamic latch permits the magazine to be inserted into the magazine...
US-8,103,940 Programming error correction code into a solid state memory device with varying bits per cell
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to...
US-8,103,936 System and method for data read of a synchronous serial interface NAND
A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from...
US-8,103,928 Multiple device apparatus, systems, and methods
Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that...
US-8,103,898 Explicit skew interface for mitigating crosstalk and simultaneous switching noise
Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface...
US-8,103,805 Configuration finalization on first valid NAND command
A startup method and circuit to allow high current consumption for startup processes of a low operating voltage memory device such as a NAND device until the...
US-8,103,752 System and method for facilitating distribution of a translator
Disclosed are systems and methods for installing translators. In one embodiment, a system and a method pertain to identifying devices that are to receive the...
US-8,103,672 Apparatus, system, and method for determining a partial class membership of a data record in a class
An apparatus, system, and method are disclosed for determining a partial class membership of a data record in a class. The apparatus includes a record set...
US-8,102,906 Fractional-rate decision feedback equalization useful in a data transmission system
Decision feedback equalization (DFE) circuits are disclosed for use with fractional-rate clocks of lesser frequency than the data signal. For example, a...
US-8,102,904 Methods and systems for data rate detection for multi-speed embedded clock serial receivers
A method of determining a data rate of a high speed serially transmitted data stream comprises statistically examining edge timing characteristics of the...
US-8,102,723 Memory device bit line sensing system and method that compensates for bit line resistance variations
Systems, devices and methods are disclosed, such as a system and method of sensing the voltage on bit lines that, when respective memory cells coupled to the...
US-8,102,715 Power-off apparatus, systems, and methods
Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as...
US-8,102,714 Programming methods for multi-level memory devices
A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate,...
US-8,102,712 NAND programming technique
A NAND memory array is programmed applying a programming voltage Vpgm as a double pulse programming pulse if a data pattern associated with memory cells that...
US-8,102,710 System and method for setting access and modification for synchronous serial interface NAND
The invention includes a system and method of modifying a setting of a NAND flash memory device using serial peripheral interface (SPI) communication from a...
US-8,102,709 Transistor having peripheral channel
Transistors for use in semiconductor integrated circuit devices including a first source/drain region of the transistor is formed around a perimeter of a...
US-8,102,707 Non-volatile multilevel memory cells
The present disclosure includes methods, devices, modules, and systems for operating non-volatile multilevel memory cells. One method embodiment includes...
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