Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: Idaho





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-7,961,495 Programmable resistance memory with feedback control
A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory...
US-7,961,488 Method for modifying data more than once in a multi-level cell memory location within a memory array
A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a...
US-7,961,292 Sub-resolution assist devices and methods
Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask...
US-7,961,127 Variable gain stage having same input capacitance regardless of the stage gain
A programmable gain amplifier (PGA) includes a sample-and-hold (S&H) stage which provides an input capacitance value for storing a charge. The PGA also includes...
US-7,961,060 Amplitude regulated resonant oscillator with sampled feedback
Disclosed is an oscillator circuit, comprising a crystal oscillator, an amplifier having an input and an output coupled across the crystal oscillator, a...
US-7,961,019 Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes...
US-7,960,829 Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the...
US-7,960,813 Programmable resistance memory devices and systems using the same and methods of forming the same
A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first...
US-7,960,803 Electronic device having a hafnium nitride and hafnium oxide film
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of...
US-7,960,797 Semiconductor devices including fine pitch arrays with staggered contacts
A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one...
US-7,960,765 Method and apparatus for providing an integrated circuit having p and n doped gates
A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and...
US-7,960,534 Thermophilic and thermoacidophilic sugar transporter genes and enzymes from alicyclobacillus acidocaldarius and...
Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from Alicyclobacillus acidocaldarius are provided. Further provided are...
US-7,960,291 Porous organosilicate layers, and vapor deposition systems and methods for preparing same
The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous...
US-7,959,975 Methods of patterning a substrate
A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is...
US-D639,899 Filter block for liquid filtration
US-D639,703 Front face of a plaque
US-7,958,491 Command line output redirection
In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method...
US-7,958,439 Defective memory block remapping method and system, and memory device and processor-based system using same
A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an...
US-7,958,246 Establishing unique sessions for DNS subscribers
A method and system for providing service over a communication network. The method includes establishing a plurality of virtual DNS servers that is supported by...
US-7,957,659 Image forming apparatus for marginless printing
Provided is an image forming apparatus in which the image forming apparatus has a marginless mode in which the toner image is formed on said image bearing...
US-7,957,215 Method and apparatus for generating temperature-compensated read and verify operations in flash memories
Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable...
US-7,957,214 Adjustable voltage regulator for providing a regulated output voltage
Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator...
US-7,957,207 Programmable resistance memory with interface circuitry for providing read information to external circuitry...
A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a...
US-7,957,206 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each...
US-7,957,198 Verifying an erase threshold in a memory device
In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory...
US-7,957,196 Method of programming memory cells of series strings of memory cells
Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after...
US-7,957,182 Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same
A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes...
US-7,957,030 Image forming apparatus for identifying undesirable toner placement
A method and apparatus for printing data on a print medium is disclosed. The apparatus is configured to format print data to pixel data, the pixel data...
US-7,957,016 Method and apparatus for image processing
A method for image processing loads a cache line width column of image data into a data cache. The cache line width column of image data is then processed to...
US-7,956,914 Imager methods, apparatuses, and systems providing a skip mode with a wide dynamic range operation
Methods, apparatuses and systems provide a high dynamic range mode of operation for an image sensor when operating in a skip mode where certain pixels of an...
US-7,956,912 Active pixel sensor with mixed analog and digital signal integration
An active pixel sensor includes mixed analog and digital signal integration on the same substrate. The analog part of the array forms the active pixel sensor,...
US-7,956,685 Adaptive operational transconductance amplifier load compensation
A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The...
US-7,956,673 Variable stage charge pump and method for providing boosted output voltage
An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage....
US-7,956,648 Output driver robust to data dependent noise
Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may...
US-7,956,443 Through-wafer interconnects for photoimager and memory wafers
A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making...
US-7,956,426 Lanthanide dielectric with controlled interfaces
Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer...
US-7,956,416 Integrated circuitry
Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material...
US-7,956,402 Double-doped polysilicon floating gate
The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method...
US-7,956,396 Memory array having floating gate semiconductor device
A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a...
US-7,955,976 Methods of forming semiconductor structures
The present invention relates to methods of forming semiconductor structures. The methods may include disposing electrically conductive material within an...
US-7,955,946 Methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit,...
The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a...
US-7,955,935 Non-volatile memory cell devices and methods
A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots,...
US-7,955,917 Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods
A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are...
US-7,955,898 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a...
US-7,955,764 Methods to make sidewall light shields for color filter array
Methods of forming color filters having a light blocking material therebetween. A color filter is formed such that a trench is defined between a color filter...
US-7,954,971 Offset mountable light accessory
An offset mountable light, including a light body, wherein the light body includes a battery compartment positioned within a cavity formed by the light body; a...
US-7,954,654 Bow caddy
A collapsible bow holder that fits over the back of a car or truck seat to facilitate the ready access to a bow in the event that a sportsman wants to deploy it...
US-7,954,409 Loading system and method for elastic projectile
A method for forming a projectile cartridge includes positioning a sabot within a compartment of a projectile cartridge casing. A delivery tube is inserted...
US-7,954,271 Firearm monopod
A monopod for a firearm is disclosed. The monopod has a body and a leg that can extend from the body. The monopod may fit into a pistol grip of a firearm, such...
US-7,954,270 Reversible rail for a firearm
A mounting rail for a firearm is disclosed. The mounting rail may be a picatinny rail, a weaver rail, or the like, which allows tools such as lights or lasers...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.