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Patent # Description
US-7,964,971 Flexible column die interconnects and structures including same
A flexible column interconnect for a microelectronic substrate includes a plurality of conductive columns extending from a bond pad or other conductive terminal...
US-7,964,946 Semiconductor package having discrete components and system containing the package
A semiconductor package includes a substrate having contacts, and a discrete component on the substrate in electrical communication with the contacts. The...
US-7,964,929 Method and apparatus providing imager pixels with shared pixel components
The disclosed embodiments employ shared pixel component architectures that arrange the shared pixel components for a group of pixels within different pixels of...
US-7,964,909 Scalable high density non-volatile memory cells in a contactless memory array
A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa...
US-7,964,503 Methods of patterning photoresist, and methods of forming semiconductor constructions
The invention includes semiconductor constructions containing optically saturable absorption layers. An optically saturable absorption layer can be between...
US-7,964,471 Methods of forming capacitors
A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and...
US-7,964,436 Co-sputter deposition of metal-doped chalcogenides
The present invention is related to methods and apparatus that allow a chalcogenide glass such as germanium selenide (Ge.sub.xSe.sub.1-x) to be doped with a...
US-7,964,290 Magnetic material with large magnetic-field-induced deformation
A magnetic materials construct and a method to produce the construct are disclosed. The construct exhibits large magnetic-field-induced deformation through the...
US-7,964,242 Formation of carbon-containing material
A method includes forming ionic clusters of carbon-containing molecules, which molecules have carbon-carbon sp.sup.2 bonds, and accelerating the clusters. A...
US-7,964,231 Coated potato substrates having reduced fat content
A food product including a potato substrate having less than about 6% moisture content that is at least partially coated with a coating composition having a...
US-7,964,124 Method of forming cellular material
Systems, devices and methods are provided that are related to cellular materials that have a precisely-determined arrangement of voids formed using surface...
US-7,964,109 Method of cleaning a surface of a cobalt-containing material, method of forming an opening to a...
The invention includes methods of cleaning a surface of a cobalt-containing material, methods of forming an opening to a cobalt-containing material,...
US-7,964,107 Methods using block copolymer self-assembly for sub-lithographic patterning
Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock...
US-D640,343 Combination desiccant/floatant storage/applicator
US-D640,181 Aircraft navigation and anti-collision light
US-D640,036 Spiral potato piece
US-7,962,784 Repairable block redundancy scheme
A scheme for block substitution within a flash memory device is disclosed which uses a programmable look-up table to store new addresses for block selection...
US-7,962,673 Method and apparatus for accessing a data bus to transfer data over the data bus
A method for intervaled memory transfer access provides periodic authorization signals to a memory access controller. The method cycles between: 1) inhibiting...
US-7,962,569 Embedded DNS
An embodiment is directed to a method for selectively routing a DNS request in which a DNS request to translate a domain name is received from a local client...
US-7,961,538 Methods for determining resistance of phase change memory elements
Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of...
US-7,961,526 Power saving sensing scheme for solid state memory
Methods and apparatus are disclosed, such as those involving a solid state memory device. One such method includes selecting a plurality of memory cells in a...
US-7,961,522 Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during...
US-7,961,518 Programming rate identification and control in a solid state memory
Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer...
US-7,961,517 Program and read trim setting
A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device...
US-7,961,507 Non-volatile memory with resistive access component
Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of...
US-7,961,506 Multiple memory cells with rectifying device
Memory devices and methods described are shown that provide improvements, including improved cell isolation for operations such as read and write. Further,...
US-7,961,495 Programmable resistance memory with feedback control
A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory...
US-7,961,488 Method for modifying data more than once in a multi-level cell memory location within a memory array
A method and apparatus for programming one or more bits in an upper page twice depending on the value in a corresponding bit in a corresponding lower page in a...
US-7,961,292 Sub-resolution assist devices and methods
Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask...
US-7,961,127 Variable gain stage having same input capacitance regardless of the stage gain
A programmable gain amplifier (PGA) includes a sample-and-hold (S&H) stage which provides an input capacitance value for storing a charge. The PGA also includes...
US-7,961,060 Amplitude regulated resonant oscillator with sampled feedback
Disclosed is an oscillator circuit, comprising a crystal oscillator, an amplifier having an input and an output coupled across the crystal oscillator, a...
US-7,961,019 Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes...
US-7,960,829 Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates
A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the...
US-7,960,813 Programmable resistance memory devices and systems using the same and methods of forming the same
A programmable resistance memory element and method of forming the same. The memory element includes a first electrode, a dielectric layer over the first...
US-7,960,803 Electronic device having a hafnium nitride and hafnium oxide film
The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium nitride (Hf.sub.3N.sub.4) and hafnium oxide (HfO.sub.2) and a method of...
US-7,960,797 Semiconductor devices including fine pitch arrays with staggered contacts
A semiconductor device structure includes staggered contacts to facilitate small pitches between active-device regions and conductive lines while minimizing one...
US-7,960,765 Method and apparatus for providing an integrated circuit having p and n doped gates
A method and apparatus providing an integrated circuit having a plurality of gate stack structures having gate oxide layers with differing thicknesses and...
US-7,960,534 Thermophilic and thermoacidophilic sugar transporter genes and enzymes from alicyclobacillus acidocaldarius and...
Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from Alicyclobacillus acidocaldarius are provided. Further provided are...
US-7,960,291 Porous organosilicate layers, and vapor deposition systems and methods for preparing same
The present invention provides porous organosilicate layers, and vapor deposition systems and methods for preparing such layers on substrates. The porous...
US-7,959,975 Methods of patterning a substrate
A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is...
US-D639,899 Filter block for liquid filtration
US-D639,703 Front face of a plaque
US-7,958,491 Command line output redirection
In one embodiment the invention provides a method to provide command line utility output to an application without the need of temporary files. The method...
US-7,958,439 Defective memory block remapping method and system, and memory device and processor-based system using same
A non-volatile memory device includes a block remapping system that offsets an input block address by the addresses of non-functional blocks to provide an...
US-7,958,246 Establishing unique sessions for DNS subscribers
A method and system for providing service over a communication network. The method includes establishing a plurality of virtual DNS servers that is supported by...
US-7,957,659 Image forming apparatus for marginless printing
Provided is an image forming apparatus in which the image forming apparatus has a marginless mode in which the toner image is formed on said image bearing...
US-7,957,215 Method and apparatus for generating temperature-compensated read and verify operations in flash memories
Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable...
US-7,957,214 Adjustable voltage regulator for providing a regulated output voltage
Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator...
US-7,957,207 Programmable resistance memory with interface circuitry for providing read information to external circuitry...
A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a...
US-7,957,206 Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each...
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