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Patent # Description
US-7,936,181 Method and circuit for off chip driver control, and memory device using same
An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is...
US-7,936,000 Vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
A vertical transistor having a wrap-around-gate and a method of fabricating such a transistor. The wrap-around-gate (WAG) vertical transistors are fabricated by...
US-7,935,999 Memory device
A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are...
US-7,935,997 Low resistance peripheral contacts while maintaining DRAM array integrity
An apparatus having low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM...
US-7,935,991 Semiconductor components with conductive interconnects
A semiconductor component includes a semiconductor substrate having at least one conductive interconnect on the backside thereof bonded to an inner surface of a...
US-7,935,950 Controllable ovonic phase-change semiconductor memory device and methods of programming the same
An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of programming the...
US-7,935,639 Process for increasing feature density during the manufacture of a semiconductor device
Methods used during the manufacture of a semiconductor device, such as one that includes forming a plurality of vertically oriented first support features. Each...
US-7,935,633 Poly etch without separate oxide decap
The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon...
US-7,935,618 Sputtering-less ultra-low energy ion implantation
Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering...
US-7,935,610 Semiconductor device isolation structures
Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a...
US-7,935,602 Semiconductor processing methods
The invention includes methods of forming isolation regions. An opening can be formed to extend into a semiconductor material, and an upper periphery of the...
US-7,935,503 Methods for producing and using polymyxins
The present invention provides methods for producing a polymyxin from an isolated Paenibacillus amylolyticus, and methods for using the polymyxin, including...
US-7,935,242 Method of selectively removing conductive material
An electrolyte solution, methods, and systems for selectively removing a conductive metal from a substrate are provided. The electrolyte solution comprising...
US-7,935,198 Glass stability, glass forming ability, and microstructural refinement
The present invention relates to the addition of niobium to iron based glass forming alloys. More particularly, the present invention is related to changing the...
US-7,935,067 Anchored ankle support
The present invention is directed to an anchored ankle brace including an anchor strap that connects an anchor member and ankle support member creating an...
US-D637,015 Adjustable support frame
US-7,934,048 Filtered register architecture to generate actuator signals
In various embodiments, apparatus and systems, as well as methods, may include an enhanced register to provide actuator signals to a memory array, the enhanced...
US-7,933,874 Maintaining tracking information for electronic documents
A plurality of parts for an electronic document are generated. The plurality of parts include a root relationship part that identifies one or more of the...
US-7,933,761 Creation of clock and data simulation vectors with periodic jitter
Methods for generating simulation vectors incorporating periodic jitter, or phase-shifted periodic jitter are disclosed. Periodic jitter, such as sinusoidal...
US-7,933,162 Row addressing
Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a...
US-7,933,142 Semiconductor memory cell and array using punch-through to program and read same
An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the...
US-7,933,140 Techniques for reducing a voltage swing
Techniques for reducing a voltage swing are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for reducing a...
US-7,932,938 Method, apparatus and system providing adjustment of pixel defect map
A method, apparatus and system that allows for the identification of defective pixels, for example, defective pixel clusters, in an imager device. The method,...
US-7,932,875 Microdisplay and interface on a single chip
A microdisplay having interface circuitry on the same silicon backplane to allow it to receive digital images and video in a variety of formats and convert same...
US-7,932,789 Frequency adjustable surface acoustic wave oscillator
A frequency adjustable surface acoustic wave oscillator uses circuitry in which the phase relationship between the corresponding input and output signals and...
US-7,932,557 Semiconductor contact device
The invention provides an advanced metallization technique for fabricating a memory cell array on a substrate. The array is fabricated by forming discrete and...
US-7,932,550 Method of forming high aspect ratio structures
An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure...
US-7,932,179 Method for fabricating semiconductor device having backside redistribution layers
Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment...
US-7,932,174 Method of making a semiconductor device having improved contacts
A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole....
US-7,932,173 Method of fabricating integrated circuitry
The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed...
US-7,932,003 Methods of forming and using reticles
Some embodiments include methods of treating reticles to provide backside masking across regions of the reticle to compensate for problems occurring during...
US-7,931,769 Method of forming temporary carrier structure and associated release techniques
A method of forming a temporary carrier structure is disclosed which includes forming a plurality of recesses in a carrier structure, the recesses extending to...
US-7,931,751 Method for purification of high purity sucrose material
A method for purifying a sucrose material already in a high purity liquid, crystalline or other form of sucrose, such as raw sugar, utilizing chromatography, or...
US-7,931,608 Pediatric splint
A splinting device for receiving and stabilizing a plurality of fingers. The splinting device has a main body having a generally rigid and planar upper surface...
US-7,931,302 Laterally extendible mud flap mounting assembly for vehicles
A mud flap mounting assembly for vehicles providing an elongate laterally extending central support beam defining a medial channel slidably carrying similar...
US-7,930,926 Determination of permeability from damping
Permeability of a fluid through a saturated material is determined by measuring the dynamic response of that saturated material to shaking vibrations and/or...
US-D636,951 Tag gun
US-7,930,657 Methods of forming photomasks
Some embodiments include methods in which a mathematical representation of a photomask construction is defined, with such representation comprising a plurality...
US-7,930,612 Error detection and correction scheme for a memory device
Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are...
US-7,930,518 Method for manipulating data in a group of processing elements to perform a reflection of the data
A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until...
US-7,929,798 Method and apparatus providing noise reduction while preserving edges for imagers
A method of reducing noise in an image including steps for obtaining a first value for a target pixel, obtaining a respective second value for each neighboring...
US-7,929,368 Variable memory refresh devices and methods
Memory devices and methods are described such as those that monitor and adjust characteristics for various different portions of a given memory device. Examples...
US-7,929,343 Methods, devices, and systems relating to memory cells having a floating body
Methods, devices, and systems are disclosed relating to a memory cell having a floating body. A memory cell includes a transistor comprising a drain and a...
US-7,929,329 Memory bank signal coupling buffer and method
A memory array contains a plurality of banks coupled to each other by a plurality of data lines. Each of the data lines is divided into a plurality of segments...
US-7,929,160 Page processing and print engine management
An exemplary device implementation includes: a manager that is capable of monitoring a process for preparing a page for printing; and a print engine that is...
US-7,929,002 System and method of projecting an image on a physical substrate using a virtual image and a virtual plane
A method of projecting an image on a physical substrate using a virtual image and a virtual plane includes generating a virtual two dimensional plane and...
US-7,928,782 Digital locked loops and methods with configurable operating parameters
A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or...
US-7,928,781 Fast measurement initialization for memory
Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be...
US-7,928,710 Voltage protection circuit for thin oxide transistors, and memory device and processor-based system using same
Devices, reference voltage generators, systems and methods may include an embodiment of a voltage regulator output transistor using a thin gate insulator to...
US-7,928,582 Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces
Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic...
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