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Patent # Description
US-7,977,962 Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
US-7,977,773 Leadframe including die paddle apertures for reducing delamination
Embodiments of the present invention provide leadframes including a die paddle including one or more apertures defined therein, and electronic packages...
US-7,977,765 Antifuse circuit with well bias transistor
An antifuse circuit includes a terminal, an antifuse transistor, and a bias transistor. The antifuse transistor is formed on a substrate. The antifuse...
US-7,977,727 Semiconductor constructions
Some embodiments include methods of reflecting ions off of vertical regions of photoresist mask sidewalls such that the ions impact foot regions along the...
US-7,977,597 Wire bonders and methods of wire-bonding
Wire bonders and methods of wire-bonding are disclosed herein. In one embodiment, a method includes attaching a wire to a terminal of a microelectronic...
US-7,977,251 High selectivity BPSG to TEOS etchant
Methods of selectively etching BPSG over TEOS are disclosed. In one embodiment, a TEOS layer may be used to prevent contamination of other components in a...
US-7,977,236 Method of forming a transistor gate of a recessed access device, method of forming a recessed transistor gate...
Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the...
US-7,977,190 Memory devices having reduced interference between floating gates and methods of fabricating such devices
A floating gate memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another and methods of fabricating the...
US-7,977,157 Methods of forming integrated circuit packages, and methods of assembling integrated circuit packages
Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region...
US-7,977,037 Photoresist processing methods
A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with...
US-7,977,017 Method to recover the exposure sensitivity of chemically amplified resins from post coat delay effect
Methods of fabricating a photomask, methods of treating a chemically amplified resist-coated photomask blank, a photomask blank resulting from the methods, and...
US-7,976,897 Thermal chemical vapor deposition methods, and thermal chemical vapor deposition systems
One embodiment thermal chemical vapor deposition method includes exposing a substrate within a chamber to first and second deposition precursors effective to...
US-7,976,023 Image capturing card shuffler
The present invention features a playing card shuffling device, which through the use of a small image capturing means, captures an image of the face value of...
US-7,975,543 Method for carrying out isometric exercise regimen
A method for isometric exercise safely reduces resting blood pressure and increases overall cardiovascular health. The method utilizes an apparatus that...
US-7,975,320 Helmet including vent and actuator assembly for moving vent shutter and methods of using same
The invention is directed to protective helmets having vents with a manually operable vent shutter and methods of using same. In one embodiment, a helmet...
US-D641,233 Container
US-7,975,294 VPN management
A client attempts to transmit a presence state to a presence server that is behind a firewall of a secure network. If the client is inside the firewall, the...
US-7,975,245 Computer-implemented methods for determining if actual defects are potentially systematic defects or...
Various computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects are provided. One...
US-7,975,094 Programmable I/O interface
The invention provides an architecture and method for implementing a programmable I/O interface. The primary function provides a generic reconfigurable...
US-7,975,083 Alignment of instructions and replies across multiple devices in a cascaded system, using buffers of...
Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the...
US-7,974,819 Methods and systems for intensity modeling including polarization
Embodiments of the present invention provide computer readable media encoded with executable instructions for modeling an intensity profile at a surface...
US-7,974,738 Robotics virtual rail system and method
A virtual track or rail system and method is described for execution by a robot. A user, through a user interface, generates a desired path comprised of at...
US-7,974,146 Wordline temperature compensation
A nonvolatile memory includes a temperature dependent read window. One or more temperature compensated wordline voltage supply circuits provide temperature...
US-7,974,129 Method and apparatus for programming flash memory
A method and apparatus that provides the ability to control programming pulses having different widths and/or voltages in a flash memory device. The widths...
US-7,973,577 Control of a variable delay line using line entry point to modify line power supply voltage
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input...
US-7,973,411 Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and...
Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance...
US-7,973,388 Semiconductor structures including square cuts in single crystal silicon
A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a...
US-7,973,370 Fully depleted silicon-on-insulator CMOS logic
A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the...
US-7,972,974 Gallium lanthanide oxide films
Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The...
US-7,972,940 Wafer processing
Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to...
US-7,972,926 Methods of forming memory cells; and methods of forming vertical structures
Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end...
US-7,972,753 Masks for microlithography and methods of making and using such masks
Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on...
US-7,972,509 Washbox
Exemplary systems and methods relating to washboxes are described.
US-7,972,485 Methods and apparatus for electromechanically and/or electrochemically-mechanically removing conductive...
Methods and apparatuses for electromechanically and/or electrochemically-mechanically removing conductive material from a microelectronic substrate. An...
US-7,972,420 Hydrogen-processing assemblies and hydrogen-producing systems and fuel cell systems including the same
Hydrogen-processing assemblies, components of hydrogen-processing assemblies, and fuel-processing and fuel cell systems that include hydrogen-processing...
US-7,971,605 Air admittance vent diaphragm assembly
An air admittance vent diaphragm assembly is disclosed. The assembly comprises a base, an annular retainer ring, and an annular malleable washer. The base has...
US-7,971,549 Hydration system for kayak integration
A hydration system for kayak integration includes a deck port configured to allow fluid passage through a deck of a kayak. The system includes a reservoir...
US-7,971,208 Developing layered platform components
Various embodiments provide for a layered approach to developing operating system platform components such as a color management system. This can be...
US-7,970,964 Methods and systems to accomplish variable width data input
Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving...
US-7,970,958 Peripheral interface alert message for downstream device
According to some embodiments, a message generated by a downstream device is received at upstream device. The message may, for example, be received via a...
US-7,970,853 System for controlled printing of a signature using web-based imaging
A controlled image including a predetermined graphic symbol, for example a signature on a check or other document, is produced in a web-based imaging...
US-7,970,103 Interrogating hidden contents of a container
According to one embodiment, a system for interrogating hidden contents of a container comprises a controller, a detector system, and a data system. The...
US-7,969,815 System and method for controlling timing of output signals
The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an...
US-7,969,814 Read command triggered synchronization circuitry
A memory READ command triggered clock synchronization mode turns on a clock synchronization circuit only for memory READ operations. The clock synchronization...
US-7,969,813 Write command and write data timing circuit and methods for timing the same
Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such...
US-7,969,810 256 Meg dynamic random access memory
A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array...
US-7,969,788 Charge loss compensation methods and apparatus
Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss...
US-7,969,783 Memory with correlated resistance
A system or device including a memory device, as well as a method of operating the memory device. Such a method includes writing a plurality of data values to a...
US-7,969,782 Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status...
US-7,969,779 Integrated circuit including memory array having a segmented bit line architecture and method of controlling...
An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit...
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