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Patent # Description
US-7,873,895 Memory subsystems with fault isolation
An exemplary memory subsystem with fault isolation comprises a first data bus routing data groupings in a lower 72 bits to a first memory expander, and a second...
US-7,873,882 Circuits and methods for repairing defects in memory devices
Some embodiments of the invention include a memory device has a number of memory segments connected to a supply source through a supply control circuit. The...
US-7,873,214 Unsupervised color image segmentation by dynamic color gradient thresholding
A method for segmenting an image includes computing a color gradient map based on an inputted image and selecting at least one initial seed of at least one pixel...
US-7,873,131 Phase splitter using digital delay locked loops
A phase splitter using digital delay locked loop (DLL) to receive complementary input clock signals to generate a plurality of output signals having different...
US-7,872,926 Input buffer and method with AC positive feedback, and a memory device and computer system using same
An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative...
US-7,872,924 Multi-phase duty-cycle corrected clock signal generator and memory having same
Memories, multi-phase clock signal generators, and methods for generating multi-phase duty cycle corrected clock signals are disclosed. For example, one such...
US-7,872,923 Low voltage sensing scheme having reduced active power down standby current
A low voltage sensing scheme reduces active power down standby leakage current in a memory device. During memory's active power down state, the leak current may...
US-7,872,920 Word line drivers in non-volatile memory device and method having a shared power bank and processor-based...
A word line driver system that utilizes a voltage selection circuit to supply one of several voltages to an output node coupled to a plurality of word line...
US-7,872,912 M+N bit programming and M+L bit read for M bit memory cells
A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage...
US-7,872,911 Non-volatile multilevel memory cells with data read of reference cells
Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of...
US-7,872,682 Eclipse elimination by monitoring the pixel signal level
An anti-eclipse circuit for an imaging sensor monitors the photo signal level output by a pixel to determine whether the photo signal corresponds to the pixel...
US-7,872,676 Methods, systems, and devices for offset compensation in CMOC imagers
Methods, devices, and systems for offset compensation in an amplifier are disclosed, wherein the amplifier inputs may be exposed to large loads from an array of...
US-7,872,507 Delay lines, methods for delaying a signal, and delay lock loops
Locked loops, delay lines and methods for delaying signals are disclosed, such as a delay line and delay lock loop using the delay line includes a series of...
US-7,872,332 Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and...
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system...
US-7,872,291 Enhanced atomic layer deposition
A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second...
US-7,872,284 Pixel with strained silicon layer for improving carrier mobility and blue response in imagers
An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag,...
US-7,871,934 Method for an integrated circuit contact
A process is provided for forming vertical contacts in the manufacture of integrated circuits and devices. The process eliminates the need for precise mask...
US-7,871,911 Methods for fabricating semiconductor device structures
Methods for fabricating semiconductor device structures are disclosed. In some embodiments, methods for fabricating semiconductor device structures may...
US-7,871,859 Vertical surface mount assembly and methods
A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier...
US-7,871,198 High-temperature thermocouples and related methods
A high-temperature thermocouple and methods for fabricating a thermocouple capable of long-term operation in high-temperature, hostile environments without...
US-7,870,891 Systems, devices and methods for regulating temperatures of tanks, containers and contents therein
The invention encompasses a temperature regulating system that includes a shell configured to be received over an outer circumferential portion of a container....
US-D631,125 Reticle for an aiming device
US-7,870,608 Early detection and monitoring of online fraud
Various embodiments of the invention provide solutions (including inter alia, systems, methods and software) for dealing with online fraud. In particular,...
US-7,870,435 Memory device and method for repairing a semiconductor memory
A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row....
US-7,870,351 System, apparatus, and method for modifying the order of memory accesses
Systems and methods for controlling memory access operation are disclosed. The system may include one or more requestors performing requests to memory devices....
US-7,870,330 Controller for refreshing memories
A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device...
US-7,870,329 System and method for optimizing interconnections of components in a multichip memory module
An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have...
US-7,869,494 Equalizer circuitry for mitigating pre-cursor and post-cursor intersymbol interference
One or more embodiments of the invention comprise a continuous-time equalizer (CTE) for reducing both pre-cursor and post-cursor intersymbol interference (ISI)...
US-7,869,457 High speed ring/bus
A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node...
US-7,869,301 Apparatus for writing to multiple banks of a memory device
In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows...
US-7,869,285 Low voltage operation bias current generation circuit
Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a...
US-7,869,249 Complementary bit PCRAM sense amplifier and method of operation
A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM...
US-7,869,242 Transmission lines for CMOS integrated circuits
Improved methods and structures are provided for impedance-controlled low-loss lines in CMOS integrated circuits. The present invention offers a reduction in...
US-7,869,091 Scanner characteristic adjustment
A method and system sense print a calibration feature towards an edge of a medium, scan the feature to determine a parameter and adjust a characteristic of the...
US-7,868,630 Integrated light conditioning devices on a probe card for testing imaging devices, and methods of fabricating same
A probe card is disclosed which includes a body, at least one housing in the body, the housing having at least one light opening, and at least one light...
US-7,868,440 Packaged microdevices and methods for manufacturing packaged microdevices
Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the...
US-7,868,369 Localized masking for semiconductor structure development
Container structures for use in integrated circuits and methods of their manufacture without the use of mechanical planarization such as chemical-mechanical...
US-7,868,310 Resistance variable memory device and method of fabrication
Methods and apparatus for providing a resistance variable memory device with agglomeration prevention and thermal stability. According to one embodiment, a...
US-7,867,919 Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer
Lanthanum-metal oxide dielectric layers and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a...
US-7,867,851 Methods of forming field effect transistors on substrates
The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect...
US-7,867,850 Enhanced multi-bit non-volatile memory device with resonant tunnel barrier
A non-volatile memory cell uses a resonant tunnel barrier that has an amorphous silicon and/or amorphous germanium layer between two layers of either HfSiON or...
US-7,867,845 Transistor gate forming methods and transistor structures
A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill...
US-7,867,844 Methods of forming NAND cell units
Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at...
US-7,867,843 Gate structures for flash memory and methods of making same
A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and...
US-7,867,335 GaN bulk growth by Ga vapor transport
GaN is grown by creating a Ga vapor from a powder, and using an inert purge gas from a source to transport the vapor to a growth site where the GaN growth takes...
US-7,866,735 Curbside loader and unloader
A bed has been provided for use with a vehicle in which the bed has a side loading apparatus and an opposite opening side wall through which material can be...
US-7,866,580 Tower support system for irrigation system
A swing arm support system for automated irrigation systems has a support hub and a means to attach and operate two wheels to opposite sides of the support hub....
US-7,866,515 Paddle platform
A paddle for securing at least one holster or accessory carrier at a desired attitude, the paddle including an attachment plate, a first arcuate slot defined...
US-7,866,491 Wall hanging garage shelf and rack storage system
A storage system capable of a variety of configurations and adaptations to be made based upon the necessities and desires of the user. The basic units of the...
US-7,865,977 Thermal goggle lens assembly with externally vented chamber
A sports goggle includes double lens goggles having inner and outer lenses joined at their perimeter by an adhesive, such as silicone, to form an air cavity. A...
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