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Patent # Description
US-7,885,782 Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed...
A method of manufacturing IC devices from semiconductor wafers includes providing the wafers and fabricating ICs on the wafers. At probe, a unique fuse ID is...
US-7,885,128 Redundant memory array for replacing memory sections of main memory
Memories and methods for replacing memory sections of a main memory array by mapping memory addresses for an entire main memory section to at least one memory...
US-7,884,724 Radio frequency data communications device with selectively removable antenna portion and method
An adjustable radio frequency data communications device has a monolithic semiconductor integrated circuit with integrated circuitry, interrogation receiving...
US-7,884,629 Probe card layout
Multi-touchdown, parallel test probe cards having probe elements arranged to provide greater efficiency during testing of a substrate having a plurality of die...
US-7,884,620 Sensor for measuring moisture and salinity
A sensor for measuring the moisture and salinity of a material is disclosed herein. The sensor preferably includes a soil moisture circuit, a soil salinity...
US-7,884,489 Press-fit integrated circuit package involving compressed spring contact beams
An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality...
US-7,884,427 Applying epitaxial silicon in disposable spacer flow
A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a...
US-7,884,405 Method for production of MRAM elements
Magneto-resistive random access memory elements include a ferromagnetic layer having uniaxial anisotropy provided by elongate structures formed in the...
US-7,884,349 Selection device for re-writable memory
A memory cell including a memory element and a non-ohmic device (NOD) that are electrically in series with each other is disclosed. The NOD comprises a...
US-7,884,311 Imaging devices having a layer of pixel component material with discrete constructs for operating electrical...
Methods and structures to reduce the occurrence of crosstalk and pixel noise in solid state imager arrays. In an exemplary embodiment, a section of a layer...
US-7,884,022 Multiple deposition for integration of spacers in pitch multiplication process
Pitch multiplication is performed using a two step process to deposit spacer material on mandrels. The precursors of the first step react minimally with the...
US-7,884,015 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using...
Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment,...
US-7,884,007 Super high density module with integrated wafer level packages
A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of...
US-7,883,986 Methods of forming trench isolation and methods of forming arrays of FLASH memory cells
This invention includes methods of forming trench isolation. In one implementation, isolation trenches are provided within a semiconductor substrate. A liquid is...
US-7,883,962 Trench DRAM cell with vertical device and buried word lines
A DRAM array having trench capacitor cells of potentially 4F.sup.2 surface area (F being the photolithographic minimum feature width), and a process for...
US-7,883,959 Semiconductor processing methods
The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a...
US-7,883,940 Ball grid array including redistribution layer, packaged integrated circuit including the same, and methods of...
Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA...
US-7,883,931 Methods of forming memory cells, and methods of forming programmed memory cells
In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region;...
US-7,883,927 Method and apparatus to sort nanotubes
Methods and systems for sorting nanostructures, such as nanodot or nanotubes, are described. The sorting of the nanostructures removes remnants of the nanotube...
US-7,883,908 Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI)
A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first...
US-7,883,907 Parameter measurement using multi-layer structures
Various embodiments disclosed herein include methods for measuring a parameter associated with a workpiece. Such a method may include providing a first overlay...
US-7,883,745 Chemical vaporizer for material deposition systems and associated methods
System and method for operating a material deposition system are disclosed. In one embodiment, the method can include periodically injecting a precursor into a...
US-7,882,596 Adjustable handle clamp systems and methods
An auxiliary handle clamp system includes an upper base, a lower base coupleable with the upper base, a handle attachment coupled with the upper base, and a...
US-D632,094 Picture frame and easel
US-7,882,306 Method for substantially uninterrupted cache readout
A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring...
US-7,882,029 Centralized billing credit system utilizing a predetermined unit of usage
Disclosed is an electronic transaction recording system for accumulating data from printer devices comprising a mobile access unit containing content which is to...
US-7,881,538 Efficient detection of constant regions of an image
A technique that improves image analysis efficiency by reducing the number of computations needed to detect constant regions. Constant region detection according...
US-7,881,149 Write latency tracking using a delay lock loop in a synchronous DRAM
A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the...
US-7,881,134 Replacing defective columns of memory cells in response to external addresses
Electronic systems and methods of operating memory devices are provided. In one such embodiment, a memory device receives an external address that addresses a...
US-7,881,113 Relaxed metal pitch memory architectures
A relaxed metal pitch architecture may include a bit line and a first active area string and a second active area string. The bit line may be directly coupled to...
US-7,881,100 State machine sensing of memory cells
The present disclosure includes methods, devices, modules, and systems for sensing memory cells using a state machine. One method embodiment includes generating...
US-7,881,094 Voltage reference generation for resistive sense memory cells
Various embodiments of the present invention are generally directed to an apparatus and associated method for generating a reference voltage for a resistive...
US-7,881,051 Memory module and cover therefor
A storage device has a memory module enclosed within a housing and a removable cover. In a first configuration of the storage device, while leaving a portion of...
US-7,880,924 Method for faxing documents printed on colored media
Methods of detecting and compensating for colored media when utilizing the facsimile send function of an All-in-One printing system are disclosed. Embodiments...
US-7,880,918 System and method for generating unified image output
A system and related techniques generate a unified representation of graphical representations, such as documents, graphic images or others, for displaying on a...
US-7,880,531 System, apparatus, and method for selectable voltage regulation
Apparatuses, systems, and methods are disclosed for generating, regulating, and modifying various voltage levels on a semiconductor device using a current...
US-7,880,307 Semiconductor device including through-wafer interconnect structure
Semiconductor devices including through-wafer interconnects are disclosed. According to an embodiment of the present invention, a semiconductor device may...
US-7,880,267 Buried decoupling capacitors, devices and systems including same, and methods of fabrication
A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a...
US-7,880,255 Pixel cell having a grated interface
A pixel cell having a photosensor within a silicon substrate; and an oxide layer provided over the photosensor, the oxide layer having a grated interface with...
US-7,880,232 Processes and apparatus having a semiconductor fin
A process may include first etching a trench isolation dielectric through a dielectric hard mask that abuts the sidewall of a fin semiconductor. The first etch...
US-7,880,168 Method and apparatus providing light traps for optical crosstalk reduction
An imager having layers of light trapping material to reduce optical crosstalk and a method of forming the same.
US-7,880,057 Precise breeding--backbone integration markers
The present invention relates to a new plant breeding process. The process improves the agronomic performance of crop plants by using genetic material that is...
US-7,879,749 Methods of using structures including catalytic materials disposed within porous zeolite materials to...
Catalytic structures include a catalytic material disposed within a zeolite material. The catalytic material may be capable of catalyzing a formation of methanol...
US-7,879,674 Germanium-silicon-carbide floating gates in memories
The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in...
US-7,879,665 Structure and method of fabricating a transistor having a trench gate
An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with...
US-7,879,659 Methods of fabricating semiconductor devices including dual fin structures
Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel...
US-7,879,649 Programmable capacitor associated with an input/output pad
The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus...
US-7,879,646 Assemblies displaying differential negative resistance, semiconductor constructions, and methods of forming...
The invention includes a device displaying differential negative resistance characterized by a current-versus-voltage profile having a peak-to-valley ratio of at...
US-7,879,638 Backside illuminated imager and method of fabricating the same
A structure and method for fabricating imagers that detect light from the backside of the wafer. The structure may have less complex focusing, reduced crosstalk,...
US-7,879,385 Emulsified bean-based oil substitute
A method for making a bean-based oil substitute comprising the steps of making an aqueous liquid dispersion of comminuted beans in a stable flowable form,...
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