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Patent # Description
US-1,015,3299 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-1,015,3298 Integrated structures and methods of forming vertically-stacked memory cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within...
US-1,015,3281 Memory cells and memory arrays
Some embodiments include a memory cell having first and second transistors and first and second capacitors. The first capacitor is vertically displaced relative...
US-1,015,3254 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing...
A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second ...
US-1,015,3251 Apparatuses and methods for scalable memory
Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and...
US-1,015,3221 Face down dual sided chip scale memory package
A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides...
US-1,015,3200 Methods of forming a nanostructured polymer material including block copolymer materials
Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods...
US-1,015,3197 Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-1,015,3196 Arrays of cross-point memory structures
Some embodiments include a memory array having a first set of lines extending along a first direction, and a second set of lines over the first set of lines and...
US-1,015,3195 Semiconductor constructions comprising dielectric material
Some embodiments include a semiconductor construction which has one or more openings extending into a substrate. The openings are at least partially filled with...
US-1,015,3194 Array of gated devices and methods of forming an array of gated devices
An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid...
US-1,015,3190 Devices, systems and methods for electrostatic force enhanced semiconductor bonding
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding...
US-1,015,3178 Semiconductor die assemblies with heat sink and associated systems and methods
Semiconductor die assemblies with heat sinks are disclosed herein. In one embodiment, a semiconductor die assembly includes a stack of semiconductor dies and a...
US-1,015,3054 Ferroelectric memory cell recovery
Methods, systems, and devices for recovering fatigued ferroelectric memory cells are described. Recovery voltages may be applied to a ferroelectric memory cell...
US-1,015,3049 Erasing memory segments in a memory block of memory cells using select gate control line voltages
A method includes applying erase voltages to data lines and source lines of a memory block of memory cells in a non-volatile NAND architecture memory device...
US-1,015,3047 Nonconsecutive sensing of multilevel memory cells
Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell...
US-1,015,3043 Methods of programming and sensing in a memory device
Methods of programming and sensing in a memory device including connecting first and second data lines in series before programming or sensing, respectively.
US-1,015,3040 Apparatuses and methods for current limitation in threshold switching memories
Apparatuses and methods for limiting current in threshold switching memories are disclosed. An example apparatus may include a plurality of first decoder...
US-1,015,3039 Memory cells programmed via multi-mechanism charge transports
The present disclosure includes memory cells programmed via multi-mechanism charge transports. An example apparatus includes a semiconductor material, a...
US-1,015,3031 Apparatuses and methods for controlling refresh operations
An apparatus includes a first word line, a second word line and a control. The second word line is contiguous to the first word line. The control circuit...
US-1,015,3030 Apparatuses and methods for configurable command and data input circuits for semiconductor memories
Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal...
US-1,015,3027 Memory arrays, and methods of forming memory arrays
Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has...
US-1,015,3026 Writing to cross-point non-volatile memory
Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a...
US-1,015,3024 Dynamic adjustment of memory cell digit line capacitance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state....
US-1,015,3023 Cell-based reference voltage generation
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be initialized to a first...
US-1,015,3022 Time-based access of a memory cell
Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a...
US-1,015,3021 Time-based access of a memory cell
Methods, systems, and devices for time-based access of memory cells in a memory array are described herein. During a sense portion of a read operation, a...
US-1,015,3020 Dual mode ferroelectric memory cell operation
Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated...
US-1,015,3019 Compensation for threshold voltage variation of memory cell components
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Before reading a memory cell, the voltage on an access line of...
US-1,015,3018 Ferroelectric memory cells
Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors....
US-1,015,3016 Apparatus of offset voltage adjustment in input buffer
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes an input pad, an input buffer including a...
US-1,015,3014 DQS-offset and read-RTT-disable edge control
Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ)...
US-1,015,3009 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-1,015,3008 Apparatuses and methods for performing corner turn operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a...
US-1,015,3007 Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region...
Apparatuses and methods related to memory arrays with separate global read and write lines and/or sense amplifier region column select lines are disclosed. An...
US-1,015,2739 Smartphone software application for identification of sound- or light-emitting vehicle accessory product models
A mobile device software app facilitates a user's identification of a product suitable for various vehicle types and operating environments. The app configures...
US-1,015,2414 Line termination methods
Methods for termination of signal lines within a memory system include appointing a particular memory device of a plurality of memory devices to act as a...
US-1,015,2374 Error code calculation on sensing circuitry
Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are...
US-1,015,2373 Methods of operating memory including receipt of ECC data
Methods of operating a memory, including receiving first data to be written to an array of memory cells of the memory, receiving error correction code (ECC)...
US-1,015,2304 Apparatuses and methods for random number generation
The present disclosure includes apparatuses and methods for random number generation. An example method includes operating a sense amplifier of a memory device...
US-1,015,2271 Data replication
The present disclosure includes apparatuses and methods for data replication. An example apparatus includes a plurality of sensing circuitries comprising...
US-1,015,2262 Memory access techniques in memory devices with multiple partitions
Methods, systems, and devices for operating a memory array are described. A memory controller may be configured to provide enhanced bandwidth on a ...
US-1,015,2237 Non-deterministic memory protocol
The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the...
US-1,015,2113 Dynamic power-down of a block of a pattern-recognition processor
A device includes a pattern-recognition processor. The pattern recognition processor includes blocks, such that each of the blocks include a plurality of...
US-1,015,1981 Methods of forming structures supported by semiconductor substrates
Some embodiments include methods of forming structures supported by semiconductor substrates. Radiation-imageable material may be formed over a substrate and...
US-1,015,1527 Method and apparatus for the multi-modal accurate temperature measurement and representation of...
Methods and systems for determining a temperature of goods in a temperature controlled unit are disclosed. Raw temperature data is received for a first...
US-1,015,0060 Device for degassing liquids
A degassing chamber is disclosed, adapted for the efficient removal of entrained gases from liquids. In a preferred embodiment the degassing chamber is combined...
US-1,014,9769 Medial to lateral uncinate joint stabilizer systems and methods
A method for stabilizing a cervical spine segment includes inserting a respective uncinate joint stabilizer into each uncinate joint along a medial-to-lateral...
US-1,014,9455 Animal feeder with insertable feed restrictor
An improved animal feeder with an insertable feed restrictor. An example embodiment includes: a barrel into which animal feed may be deposited, the barrel...
US-1,014,8982 Video compression using perceptual modeling
Disclosed are techniques for video stream compression. A motion predicted frame and a current frame of video data are converted from a source color space to a...
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