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Patent # Description
US-9,343,670 Memory arrays and methods of forming same
Memory arrays and methods of forming the same are provided. One example method of forming a memory array can include forming a first conductive material having...
US-9,343,669 Semiconductor structures and devices including conductive lines and peripheral conductive pads
Semiconductor devices and structures, such as phase change memory devices, include peripheral conductive pads coupled to peripheral conductive contacts in a...
US-9,343,665 Methods of forming a non-volatile resistive oxide memory cell and methods of forming a non-volatile resistive...
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal...
US-9,343,506 Memory arrays with polygonal memory cells having specific sidewall orientations
Some embodiments include a memory array having a first series of access/sense lines which extend along a first direction, a second series of access/sense lines...
US-9,343,479 Three-dimensional devices having reduced contact length
Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with...
US-9,343,469 Three dimensional NAND flash with self-aligned select gate
An integrated circuit may include a pillar of semiconductor material, a field effect transistor having a channel that is formed in the pillar of semiconductor...
US-9,343,462 Thyristor-based memory cells, devices and systems including the same and methods for forming the same
Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F.sup.2, and methods for forming the same are provided....
US-9,343,368 Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are...
US-9,343,362 Microelectronic devices with through-silicon vias and associated methods of manufacturing
Microelectronic devices with through-silicon vias and associated methods of manufacturing such devices. One embodiment of a method for forming tungsten...
US-9,343,317 Methods of forming silicon-containing dielectric materials and semiconductor device structures
A method of forming a silicon-containing dielectric material. The method includes forming a plasma comprising nitrogen radicals, absorbing the nitrogen radicals...
US-9,343,316 Methods of forming memory cells with air gaps and other low dielectric constant materials
Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a...
US-9,343,184 Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store...
US-9,343,180 Switched interface for stacked-die memory architecture with redundancy for substituting defective memory cells
Systems and methods disclosed herein include those that may receive a memory request including a requested memory address and may send the memory request...
US-9,343,173 Semiconductor device and control method of the same
A semiconductor device comprises a bit determination circuit to count the number of bits at a first level in an input address signal formed of a plurality of...
US-9,343,169 Architecture and method for memory programming
Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is...
US-9,343,168 Multiple step programming in a memory device
Method of operating a memory include programming a memory cell and reading the memory cell to determine a programmed threshold voltage of the memory cell. If...
US-9,343,155 Memory as a programmable logic device
Methods for programming, methods for operating, and memories are disclosed. One such method for programming includes programming a group of memory cells such...
US-9,343,149 Enhancing nucleation in phase-change memory cells
Various embodiments disclosed herein comprise methods and apparatuses for placing phase-change memory (PCM) cells of a memory array into a temperature regime...
US-9,343,146 Apparatuses and methods for low power current mode sense amplification
Memory apparatuses and methods for low power current mode sense amplification are disclosed. An example memory apparatus may include a current mode sense...
US-9,343,145 Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and...
Embodiments disclosed include memory cell operating methods, memory cell programming methods, memory cell reading methods, memory cells, and memory devices. In...
US-9,343,133 Apparatuses and methods for setting a signal in variable resistance memory
An example of a method reads a spin torque transfer (STT) memory cell, and writes the STT memory cell using information obtained during the reading of the STT...
US-9,343,116 Providing power availability information to memory
The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a...
US-9,343,114 Memory arrays and methods of forming electrical contacts
Some embodiments include methods of forming electrical contacts. A row of semiconductor material projections may be formed, with the semiconductor material...
US-9,342,876 Methods, apparatuses, and computer-readable media for projectional morphological analysis of N-dimensional signals
Embodiments discussed herein in the form of methods, systems, and computer-readable media deal with the application of advanced "projectional" morphological...
US-9,342,443 Systems and methods for memory system management based on thermal information of a memory system
Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a...
US-9,342,371 Boot partitions in memory devices and systems
The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of...
US-9,341,981 Printer with integrated toner container
In one example, a printer includes a printer housing, a photoconductor to apply toner to a print substrate, a developer to apply toner to the photoconductor, a...
US-9,341,787 Apparatus providing simplified alignment of optical fiber in photonic integrated circuits
A structure for optically aligning an optical fiber to a photonic device and method of fabrication of same. The structure optically aligns an optical fiber to...
US-9,340,382 Printing device with media path flushing
A method and article determine a greatest distance between adjacent sensors along the media path and command a flushing to advance media the determined greatest...
US-D756,435 Camera housing with camera
US-D756,340 Mobile phone case
US-RE46,005 Method and apparatus for enabling a timing synchronization circuit
A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to...
US-9,338,733 Method and apparatus for determining the availability of a first device in a wireless network to provide a...
Systems, methods, and other embodiments associated with determining the availability of a first device in a wireless network to provide a service to a second...
US-9,338,413 Imaging systems with image pixels having adjustable spectral responses
An imaging system may include an image sensor having an array of image pixels. Some image pixels in the array may be provided with spectral response adjustment...
US-9,338,350 Image sensors with metallic nanoparticle optical filters
An imaging system may include one or more optical filters that include metallic nanoparticles in a matrix. The metallic nanoparticle optical filters may form a...
US-9,337,807 Output driver circuit with auto-equalization based on drive strength calibration
Systems and methods for equalizing an output driver circuit based on information from calibration of the output impedance of the driver circuit are disclosed....
US-9,337,776 High-input common-mode differential amplifiers
The present invention discloses a level-shifting circuit to provide an initial stage to a differential amplifier circuit, a differential amplifier circuit, and...
US-9,337,366 Textured optoelectronic devices and associated methods of manufacture
Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state...
US-9,337,333 Transistors with an extension region having strips of differing conductivity type
A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions...
US-9,337,266 Methods and apparatuses including an active area of a tap intersected by a boundary of a well
Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a...
US-9,337,237 Methods, structures and devices for increasing memory density
Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different...
US-9,337,210 Vertical ferroelectric field effect transistor constructions, constructions comprising a pair of vertical...
A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating...
US-9,337,201 Memory cells, arrays of memory cells, and methods of forming memory cells
A memory cell includes a vertically oriented transistor having an elevationally outer source/drain region, an elevationally inner source/drain region, and a...
US-9,337,178 Method of forming an ESD device and structure therefor
In one embodiment, an ESD device is configured to include a trigger device that assists in forming a trigger of the ESD device. The trigger device is configured...
US-9,337,162 Multi-component integrated circuit contacts
An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a...
US-9,337,119 Stacked semiconductor die assemblies with high efficiency thermal paths and associated systems
Semiconductor die assemblies having high efficiency thermal paths. In one embodiment, a semiconductor die assembly comprises a package support substrate, a...
US-9,337,064 Methods of protecting peripheries of in-process semiconductor wafers and related in-process wafers and systems
Methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material,...
US-9,337,053 Method of forming contacts for a memory device
The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a...
US-9,337,042 Method for fabricating a metal high-k gate stack for a buried recessed access device
A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain...
US-9,336,907 Pressure-tube reactor with coolant plenum
A pressure-tube nuclear reactor can include an outer shell having an interior to contain a moderator at a first pressure and a coolant plenum to receive the...
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