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Patent # Description
US-9,484,196 Semiconductor structures including liners comprising alucone and related methods
A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and...
US-9,484,101 Methods of programming memories
Methods of programming memories include applying a first plurality of programming pulses to the group of memory cells to program first data to the group of...
US-9,484,100 Memory devices having source lines directly coupled to body regions and methods
Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body...
US-9,484,088 Permutational memory cells
Various embodiments include at least one resistance change memory (RCM) cell, In one embodiment, three or more pairs of electrical contacts are coupled to the...
US-9,484,074 Current mode sense amplifier with load circuit for performance stability
Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled...
US-9,484,070 Apparatuses supporting multiple interface types and methods of operating the same
Apparatuses supporting multiple interface types and methods operating the same are described. One such method can include providing, to a memory device, a first...
US-9,483,632 Intelligent controller system and method for smart card memory modules
A storage device contains a smart-card device and a memory device, both of which are accessed though a controller. The storage device may be used in the same...
US-9,483,399 Sub-OS virtual memory management layer
A binary memory image in system is modified. The system may or may not already have virtual memory management enabled. Virtual memory management is enabled...
US-9,483,370 Error detection/correction based memory management
The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read...
US-9,483,203 Temporary mirroring, logical segregation, and redundant programming or addressing for solid state drive operation
The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that...
US-9,482,483 Firearm with integrated suppressor
Firearms with integrated suppressors have a receiver having a forward portion defining an internal bore, a tubular body having sides defining an interior, a...
US-9,481,614 Energetic materials and methods of tailoring electrostatic discharge sensitivity of energetic materials
An energetic material comprising an elemental fuel, an oxidizer or other element, and a carbon nanofiller or carbon fiber rods, where the carbon nanofiller or...
US-9,481,582 Nanocrystal synthesis
A method of preparing monodisperse MX semiconductor nanocrystals can include contacting an M-containing precursor with an X donor to form a mixture, where the...
US-9,480,941 Apparatus and method for cleaning air filters
An apparatus for cleaning air filters utilizes a pressurized fluid flow, preferably air, to rotate a set of air spraying jets inside a hollow interior of a...
US-9,480,865 Fall arrest system
A fall arrest system adapted for use in construction projects with wall studs of various spacing. The fall arrest system comprises a wall attachment bracket and...
US-9,479,830 System and method for delivering media content at predetermined times
A method and system for delivering media content to a user at predetermined times. A processing unit of the system receives streamed media content data and...
US-9,479,679 Capturing a scan line with two colors
A scanner is disclosed. The scanner has three lights with three different colors. The scanner uses only two of the three lights when capturing each scan line....
US-9,479,361 Method and apparatus for selecting an operating mode based on a determination of the availability of internal...
A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die...
US-9,479,167 Apparatuses and methods for line charge sharing
Apparatuses and methods for charge sharing, between signal lines are disclosed. An example apparatus may include first and second lines and a charge sharing...
US-9,479,151 Apparatuses and methods for controlling delay circuits during an idle state to reduce degradation of an...
Delay circuits may be controlled by apparatuses and methods during an idle state to reduce degradation of an electrical characteristic. An example apparatus...
US-9,478,929 Light bulb receptacles and light bulb sockets
Light bulb receptacles and light bulb sockets are described. According to one aspect, a light bulb receptacle includes a housing which defines a housing...
US-9,478,740 Switching device structures and methods
Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a...
US-9,478,735 Magnetic tunnel junctions
Some embodiments include a magnetic tunnel junction which has a conductive first magnetic electrode containing magnetic recording material, a conductive second...
US-9,478,643 Memory structure with self-aligned floating and control gates and associated methods
A memory structure having at least substantially aligned floating and control gates. Such a memory structure can include a control gate material disposed...
US-9,478,550 Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors
An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an...
US-9,478,502 Device identification assignment and total device number detection
Various embodiments comprise apparatuses to assign a respective one of a sequence of unique device identification (ID) values to each die in a stacked device....
US-9,478,497 Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures
Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n.gtoreq.2, tiers of stacked mandrels are...
US-9,478,426 Semiconductor device and manufacturing method thereof
A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying...
US-9,478,282 State determination in resistance variable memory
An evaluation signal is applied to a memory cell in an array of resistance variable memory cells. The evaluation signal is configured to cause the memory cell...
US-9,478,270 Data paths using a first signal to capture data and a second signal to output data and methods for providing data
Data paths, memories, and methods for providing data from memory are disclosed. An example read data path includes a delay path, and a clocked data register....
US-9,478,262 Semiconductor device including input/output circuit
Disclosed here is an apparatus that comprises a data terminal, a data output circuit including a plurality of output buffers coupled in common to the data...
US-9,477,968 Collecting information regarding consumer click-through traffic
A method and system for providing the centralized collection of click-through traffic information. The method includes receiving a DNS query for a domain name...
US-9,477,863 Systems and methods to determine motion parameters using RFID tags
Systems and methods to determine motion parameters of physical objects using radio frequency identification (RFID) tags attached to the objects. In one...
US-9,477,636 Memory having internal processors and data communication methods in memory
Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may...
US-9,477,616 Devices, systems, and methods of reducing chip select
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
US-9,477,587 Method and apparatus for a volume management system in a non-volatile memory device
Embodiments for partitioning a non-volatile memory device is described. In one embodiment a memory system includes a first addressable range of memory blocks...
US-9,477,333 Multi-touch manipulation of application objects
The manipulation system described herein provides a common platform and application-programming interface (API) for applications to communicate with various...
US-9,475,660 Palletizer for corrugated bundles
Techniques that palletize bundles at high-speed. A robotic controller includes a vision system that determines a location and orientation of incoming bundles, a...
US-9,473,465 Lingual transformation based encryption
For lingual transformation-based encryption, a method parses a secure message into lingual units. The method further generates a validation nonce from the...
US-9,473,146 Apparatuses and methods for low power counting circuits
Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an...
US-9,472,755 Resistive memory architectures with multiple memory cells per access device
A resistive memory structure, for example, phase change memory structure, includes one access device and two or more resistive memory cells. Each memory cell is...
US-9,472,699 Energy harvesting devices, systems, and related methods
Energy harvesting devices include a substrate and a plurality of resonance elements coupled to the substrate. Each resonance element is configured to collect...
US-9,472,663 N-type field effect transistors, arrays comprising N-type vertically-oriented transistors, methods of forming...
An n-type field effect transistor includes silicon-comprising semiconductor material comprising a pair of source/drain regions having a channel region...
US-9,472,560 Memory cell and an array of memory cells
A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and...
US-9,472,542 DRAM arrays, semiconductor constructions and DRAM array layouts
Some embodiments include a DRAM array layout. Wordlines extend along a first direction, and bitlines extend along a second direction that crosses the first...
US-9,472,518 Semiconductor structures including carrier wafers and methods of using such semiconductor structures
A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars...
US-9,472,461 Double gated 4F2 dram CHC cell and methods of fabricating the same
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein...
US-9,472,458 Method of reducing residual contamination in singulated semiconductor die
In one embodiment, semiconductor die are singulated from a semiconductor wafer by placing the semiconductor wafer onto a carrier tape, forming singulation lines...
US-9,472,287 Local self-boost using a plurality of cut-off cells on a single side of a string of memory cells
Methods for local self-boost of a selected memory cell channel, memory devices, and systems are disclosed. One such method generates a cut-off channel under...
US-9,472,273 Method and apparatus for decoding memory
A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such...
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