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Patent # Description
US-D755,284 Printer
US-D755,184 In line smart print module including a display
US-9,326,430 Device for cooling an electronic component in a data center
A device for cooling an electronic component in a data center is provided. The device includes a closed loop, a first area, a second area, and a barrier. The...
US-9,326,338 Multi-junction solid state transducer devices for direct AC power and associated systems and methods
Multi-junction solid-state transducer (SST) devices and associated systems and methods are disclosed herein. In several embodiments, for example, an SST system...
US-9,325,330 Semiconductor device including a clock adjustment circuit
Disclosed herein is a semiconductor device that includes a first circuit comprising a plurality of first logic elements coupled in cascade and configured, in...
US-9,324,945 Memory cells and methods of forming memory cells
A method of forming a memory cell includes forming an outer electrode material elevationally over and directly against a programmable material. The programmable...
US-9,324,943 Filamentary memory devices and methods
Apparatus, devices, systems, and methods are described that include filamentary memory cells. Mechanisms to substantially remove the filaments in the devices...
US-9,324,905 Solid state optoelectronic device with preformed metal support substrate
A wafer-level process for manufacturing solid state lighting ("SSL") devices using large-diameter preformed metal substrates is disclosed. A light emitting...
US-9,324,755 Image sensors with reduced stack height
An imaging system may include an image sensor die stacked on top of a digital signal processor (DSP) die. The image sensor die may be a backside illuminated...
US-9,324,721 Pitch-halving integrated circuit process
A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or...
US-9,324,690 Signal delivery in stacked device
Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a...
US-9,324,676 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of...
US-9,324,611 Corrosion resistant via connections in semiconductor substrates and methods of making same
Devices and methods for protecting the metal within a via in a semiconductor substrate from corrosion are provided. Specifically, embodiments of the present...
US-9,324,434 Determining memory page status
The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status...
US-9,324,423 Apparatuses and methods for bi-directional access of cross-point arrays
The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of...
US-9,324,410 Semiconductor memory device having an output buffer controller
A device includes a data output terminal, an output buffer including n first transistors (n is a natural number greater than 1) connected in parallel with the...
US-9,324,398 Apparatuses and methods for targeted refreshing of memory
Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines...
US-9,324,391 Dual event command
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-9,324,130 First image and a second image on a display
A first image and a second image of the first image. A display to display the first image and the second image. A sensor to detect an input relative to the...
US-9,324,072 Bit-flipping memory controller to prevent SRAM data remanence
A memory is organized into blocks. In a bit-flipping operation, a memory block is read, the read bit data values are inverted, and the inverted data is written...
US-9,323,994 Multi-level hierarchical routing matrices for pattern-recognition processors
Multi-level hierarchical routing matrices for pattern-recognition processors are provided. One such routing matrix may include one or more programmable and/or...
US-9,323,608 Integrity of a data bus
A method for improving data bus integrity includes a selectable data bus integrity feature that can improve the integrity of a data bus in a memory system. An...
US-9,322,851 Current-monitoring apparatus
A local area networking apparatus comprises a power stage for connecting to a network cable for carrying power and data. The power stage comprises a main...
US-9,322,503 Nondestructive refurbishment of underground pipes
A method for refurbishing an existing expandable host pipe. An expansion tool is adapted to generate isolated outward radial force when in expansion mode. The...
US-9,322,187 Sherpa--a supporting and lifting apparatus and method
The Sherpa is the ultimate sheet supporter. It is an apparatus with a method for assembling, supporting, and lifting sheet metal panels and insulation while...
US-9,320,583 Burr with floating guard
Accordingly, embodiments of the presently described system and method include an equine dentistry burr with a head having a first end and a second end. Some...
US-9,320,514 Suture anchor
A method of forming a suture anchor comprising a one piece blank folded to form a body. The body has a floor, a first sidewall extending from one end of the...
US-9,320,356 Tamper-resistant and easy-access utility pedestal
A protective device for housing utility equipment is tamper-resistant and allows easy access to the equipment for maintenance. A slidable mounting unit is...
US-D754,499 Forked extractor device
US-9,319,349 Encapsulation enabled PCIE virtualisation
There is herein described a method for transmitting data packets from a first device through a switch to a second device. The method is performed at an...
US-9,318,699 Resistive memory cell structures and methods
Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first...
US-9,318,493 Memory arrays, semiconductor constructions, and methods of forming semiconductor constructions
Some embodiments include memory arrays. The memory arrays may have digit lines under vertically-oriented transistors, with the digit lines interconnecting...
US-9,318,438 Semiconductor structures comprising at least one through-substrate via filled with conductive materials
A method for selectively removing material from a substrate without damage to copper filling a via and extending at least partially through the substrate. The...
US-9,318,430 Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components,...
A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion...
US-9,318,416 Semiconductor device including conductive layer with conductive plug
Some embodiments include a semiconductor device which includes a first conductive layer formed on the semiconductor substrate and a first contact plug connected...
US-9,318,394 Apparatus and methods for through substrate via test
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side...
US-9,318,387 Method for separating and transferring IC chips
A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of...
US-9,318,321 Methods of fabricating memory devices having charged species
Methods for fabricating memory devices having charged species. In one such method, a dielectric material is formed adjacent to a semiconductor. A charged...
US-9,318,220 Memory cell coupling compensation
Methods for memory cell coupling compensation and apparatuses configured to perform the same are described. One or more methods for memory cell coupling...
US-9,318,211 Apparatuses and methods including memory array data line selection
Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to...
US-9,318,205 Mapping between program states and data patterns
The present disclosure includes methods and apparatuses for mapping between program states and data patterns. One method includes: programming a group of G...
US-9,318,200 Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second...
Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first...
US-9,318,199 Partial page memory operations
Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data...
US-9,318,187 Method and apparatus for sensing in a memory
A method and a memory for sensing a state of a memory cell while the memory cell capacitor is isolated from a data line are described. An activation device of...
US-9,318,173 Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing...
Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the...
US-9,318,157 Stacked device detection and identification
Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by...
US-9,317,459 Memory device distributed controller system
A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an...
US-9,317,450 Security protection for memory content of processor main memory
Subject matter disclosed herein relates to memory devices and security of same.
US-9,316,014 Lever viscoelastic damping wall assembly
A lever viscoelastic damping wall assembly includes a first wall, a second wall and a viscoelastic damper. The first and second walls are connected respectively...
US-9,315,609 Thermal anneal of block copolymer films with top interface constrained to wet both blocks with equal preference
Methods for fabricating sub-lithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods...
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