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Patent # Description
US-9,444,469 Locked-loop quiescence apparatus, systems, and methods
Apparatus, systems, and methods disclosed herein may initialize a delay-locked loop (DLL) or phase-locked loop (PLL) to achieve a locked condition and may then...
US-9,444,046 Three dimensional memory array architecture
Three dimensional memory array architectures and methods of forming the same are provided. An example memory array can include a stack comprising a plurality of...
US-9,444,043 Method, system and device for phase change memory with shunt
Embodiments disclosed herein may relate to forming a storage component comprising a phase change material and a shunt relative to amorphous portions of the...
US-9,444,042 Memory cells and methods of forming memory cells
Some embodiments include a memory cell that has an electrode, a switching material over the electrode, a buffer region over the switching material, and an ion...
US-9,444,014 Solid state lighting devices with accessible electrodes and methods of manufacturing
Various embodiments of light emitting dies and solid state lighting ("SSL") devices with light emitting dies, assemblies, and methods of manufacturing are...
US-9,443,864 Self-aligned floating gate in a vertical memory structure
A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body...
US-9,443,834 Back-to-back solid state lighting devices and associated methods
Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can...
US-9,443,823 Semiconductor device including filling material provided in space defined by three semiconductor chips
A semiconductor device comprises a wiring substrate, first and second semiconductor chips mounted on the wiring substrate so as to be spaced apart from each...
US-9,443,763 Methods for forming interconnections between top electrodes in memory cells by a two-step chemical-mechanical...
Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a...
US-9,443,756 Methods of forming a substrate opening
A method of forming a substrate opening includes forming a plurality of side-by-side openings in a substrate. At least some of immediately adjacent side-by-side...
US-9,443,744 Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods
A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a...
US-9,443,733 Method and apparatus for authenticating a semiconductor die
The present disclosure describes apparatuses and techniques for device-based die authentication. In some aspects, an intensity of a particle beam is varied...
US-9,443,615 Methods and apparatuses for memory testing with data compression
Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of...
US-9,443,610 Leakage current detection
A system includes a first switch, an amplifier, a second switch, and a capacitor. The first switch is electrically coupled between a first reference voltage and...
US-9,443,573 Semiconductor device including main amplifers between memory cell arrays
A semiconductor device includes a plurality of main amplifiers provided between memory cell arrays. One of the main amplifiers is disposed closer to one of the...
US-9,443,562 Connections for memory electrode lines
Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line...
US-9,443,156 Methods and systems for data analysis in a state machine
A state machine engine may be configured to recognize (e.g., detect) a great number of patterns in a data stream. This may be accomplished via detection cells...
US-9,442,867 Interrupted write memory operation in a serial interface memory with a portion of a memory address
Subject matter disclosed herein relates to read and write processes of a memory device.
US-9,442,866 Self-adaptive solid state drive controller
A memory device may comprise circuitry to determine a number of channels through which to transfer information to adjust between latency and throughput in...
US-9,442,796 Memory controller supporting rate-compatible punctured codes
Apparatus and methods store data in a non-volatile solid state memory device according to a rate-compatible code, such as a rate-compatible convolutional code...
US-9,442,658 Apparatuses and methods including selectively providing a single or separate chip select signals
Apparatus and methods are disclosed herein, including those that operate to initialize registers of a first memory device and a second memory device of a...
US-9,442,625 Visual indication of a device connection speed
A method of providing visual indication of a device connection speed proceeds by determining a connection speed of the device and selecting a visual indicator...
US-D766,446 Medical level device
US-D766,354 String instrument end pin support
US-D765,996 Personal viewing device
US-9,438,868 Adaptive image sensor systems and methods
An imaging device may include a primary imaging sensor and a secondary imaging sensor. The secondary imaging sensor may monitor a scene being imaged by the...
US-9,437,816 Phase change memory structures and methods
A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a...
US-9,437,809 Memory cell having nonmagnetic filament contact and methods of operating and fabricating the same
A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes...
US-9,437,762 Elevated pocket pixels, imaging devices and systems including the same and method of forming the same
An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including,...
US-9,437,687 III-nitride based semiconductor structure
The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor...
US-9,437,686 Gallium nitride devices with discontinuously graded transition layer
The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor...
US-9,437,608 Vertical memory cell string with dielectric in a portion of the body
Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the...
US-9,437,604 Methods and apparatuses having strings of memory cells including a metal source
Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of...
US-9,437,480 Methods of forming semiconductor structures including tight pitch contacts and lines
Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating...
US-9,437,442 Methods for polishing phase change materials
A slurry for polishing a phase change material, such as Ge--Sb--Te, or germanium-antimony-tellurium (GST), includes abrasive particles of sizes that minimize at...
US-9,437,316 Continuous adjusting of sensing voltages
The present disclosure includes apparatuses and methods for continuous adjusting of sensing voltages. A number of embodiments include continuously monitoring an...
US-9,437,304 Memory devices and programming memory arrays thereof
An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first...
US-9,437,294 Resistance variable memory sensing
The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell...
US-9,437,288 Dual mode clock and data scheme for memory programming
A Phase-Change Memory (PCM) includes a factory programming interface to receive data changing on both a positive transition and a negative transition of a dual...
US-9,437,287 Methods, devices and processes for multi-state phase change devices
Devices include multiple phase change materials connected in parallel between electrodes. Memory cells with multiple parallel phase change materials can be...
US-9,437,265 Semiconductor device having shallow trench isolation and gate groove
Semiconductor devices have a substrate including first and second regions of differing conductivity types and a shallow trench isolation isolation region that...
US-9,437,263 Apparatuses and methods for providing strobe signals to memories
Apparatuses and methods for providing strobe signals to memories are described herein. An example apparatus may include a plurality of memories and a memory...
US-9,437,256 Data shifting
The present disclosure includes apparatuses and methods related to data shifting. An example apparatus comprises a first memory cell coupled to a first sense...
US-9,437,254 Method of dynamically selecting memory cell capacity
A method is provided for using a multi-level cell memory device. The method includes writing first data to a first portion of a memory array using a first...
US-9,437,253 Memory devices having data lines included in top and bottom conductive lines
Some embodiments include apparatuses and methods having a first set of conductive lines, a second set of conductive lines, and memory cells located in different...
US-9,437,080 Apparatus for generating alternative gaming device outputs
An apparatus for outputting an alternative output through an electronic gaming device output device has been developed. The invention includes an electronic...
US-9,436,609 Block addressing for parallel memory arrays
Apparatus and methods provide associative mapping of the blocks of two or more memory arrays such that data, such as pages of data, from the good blocks of the...
US-9,436,466 Blank bit and processor instructions employing the blank bit
Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors...
US-9,436,402 Methods and apparatus for pattern matching
Methods and apparatus for pattern matching are disclosed. In at least one embodiment, pattern checking is accomplished by reading a page of memory, and...
US-9,435,835 Validation of electric power system monitoring systems
The present disclosure provides systems and methods for validating electric power delivery monitoring systems, including, but not limited to, current...
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