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Patent # Description
US-9,269,730 Imaging systems with backside isolation trenches
An image sensor such as a backside illumination image sensor may be provided with analog circuitry, digital circuitry, and an image pixel array on a...
US-9,269,716 Method of manufacturing semiconductor device having embedded conductive line
Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second...
US-9,269,700 Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods
Stacked semiconductor die assemblies with improved thermal performance and associated systems and methods are disclosed herein. In one embodiment, a...
US-9,269,695 Semiconductor device assemblies including face-to-face semiconductor dice and related methods
Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and...
US-9,269,646 Semiconductor die assemblies with enhanced thermal management and semiconductor devices including same
A semiconductor die assembly comprises a plurality of semiconductor dice in a stack. Another semiconductor die is adjacent to the stack and has a region, which...
US-9,269,586 Selective metal deposition over dielectric layers
Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a...
US-9,269,452 Determining system lifetime characteristics
Methods and systems for determining system lifetime characteristics are described. A number of embodiments include a number of memory devices and a controller...
US-9,269,450 Methods, devices, and systems for adjusting sensing voltages in devices
The present disclosure includes methods, devices, and systems for adjusting sensing voltages in devices. One or more embodiments include memory cells, and a...
US-9,269,432 Memory systems and memory programming methods
Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of...
US-9,269,431 Configurable reference current generation for non volatile memory
This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory...
US-9,269,410 Leakage measurement systems
Described examples include leakage measurement systems and methods for measuring leakage current between a word line at a boosted voltage and a word line at a...
US-9,269,403 Independent control of stacked electronic modules
Various embodiments of apparatuses are disclosed to allow independent control of stacked modules. In one embodiment, an apparatus may include a plurality of...
US-9,268,989 Capacitive sensor packaging
An apparatus comprises a fingerprint sensor having a set of capacitive elements configured for capacitively coupling to a user fingerprint. The fingerprint...
US-9,268,690 Circuits and methods for providing data to and from arrays of memory cells
A memory device uses a global input/output line or a pair of complementary global input/output lines to couple write data signals and read data signals to and...
US-9,268,629 Dual mapping between program states and data patterns
The present disclosure includes methods and apparatuses for dual mapping between program states and data patterns. One apparatus includes a memory and a...
US-9,268,506 Methods and apparatus for determining the status of a peripheral device using a coupling device that interfaces...
Embodiments of the present disclosure provide a method comprising coupling an apparatus to a peripheral device and coupling the apparatus to a computing device....
US-9,268,354 Lever assemblies and methods
Lever assemblies are provided that can include: an enclosure; a lever pivotably coupled to the enclosure; one member extending from one end to another end, the...
US-9,268,210 Double-exposure mask structure and photolithography method thereof
Double-exposure mask structure and photolithography method for performing a photolithography process on a substrate are provided. The substrate has a central...
US-9,267,980 Capacitance evaluation apparatuses and methods
Apparatus and methods for evaluating leakage currents of capacitances are described. Capacitances having excessive leakage currents may be disabled from use. An...
US-9,267,769 Horizontal stand assembly
A horizontal stand assembly enables a user to mount a target for shooting which can be easily repaired, relocated or stored. The horizontal stand assembly...
US-9,267,372 Replaceable arbor tool holder for replaceable impact tools
A replaceable arbor tool holder for replaceable impact tools provides a base structurally carrying a tool holder for a replaceable impact tool. The base is...
US-9,267,099 Engineered lumenized vascular networks and support matrix
Disclosed herein are capillary fabrication devices comprising living cells within a support medium. Culture of the cells produces viable lumenized capillary...
US-9,265,995 Golf club head
An iron-type golf club head is disclosed having a heel portion, a sole portion, a toe portion, a top-line portion, a front portion, a rear portion, and a...
US-9,265,323 Modular decorative headband
A decorative headband having modular detachable decorative ribbons or other attachments. The wearer may select such attachments to accessorize to selected...
US-9,265,267 Open top liquid/gas cyclone separator tube and process for same
Open top liquid/gas cyclone separator tube with a dual purpose single separator tube with both liquid and gas separation zones, an open top discharge vent to...
US-9,265,211 Inbred corn line SHY 084-5055
The invention provides seed and plants of sweet corn line SHY 084-5055. The invention thus relates to the plants, seeds and tissue cultures of sweet corn line...
US-9,264,629 Suppressing flicker in digital images
Suppressing flicker in digital images includes deriving pixel values from a non-content area of a digital image, estimating flicker values within the...
US-9,264,068 Deflate compression algorithm
A compression algorithm replaces duplicative strings with a copy pair indicating a location and length of a preceding identical string that is within a window...
US-9,264,050 Apparatuses and methods for delaying signals using a delay line with homogenous architecture and integrated...
Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a...
US-9,264,029 Clock cycle compensator and the method thereof
One aspect of the present invention is to provide a method for compensating a system duty cycle of a system clock signal. The method in one embodiment comprises...
US-9,264,025 Glitch filter and filtering method
A glitch filter is disclosed herein. The glitch filter includes a high glitch filter circuit, a low glitch filter and a control circuit. The high glitch filter...
US-9,263,675 Switching components and memory units
Some embodiments include a switching component which includes a selector region between a pair of electrodes. The selector region contains silicon doped with...
US-9,263,674 ETCH bias homogenization
Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization...
US-9,263,672 Transistors, memory cells and semiconductor constructions
Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within...
US-9,263,577 Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row...
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain...
US-9,263,461 Apparatuses including memory arrays with source contacts adjacent edges of sources
Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device...
US-9,263,460 Methods and apparatuses including a select transistor having a body region including monocrystalline...
Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select...
US-9,263,459 Capping poly channel pillars in stacked circuits
A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition...
US-9,263,455 Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines
An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material...
US-9,263,341 Methods of forming transistors
Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with...
US-9,263,317 Method of forming buried word line structure
A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate,...
US-9,263,133 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory...
US-9,263,130 Memory device page buffer configuration and methods
Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry...
US-9,263,128 Methods and apparatuses for programming memory cells
Methods and apparatus for programming memory cells in a memory array are disclosed. A most recent programming time is determined, the most recent programming...
US-9,263,115 Semiconductor device
A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse...
US-9,263,111 Sub-block disabling in 3D memory
Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of...
US-9,263,104 Semiconductor device
Disclosed herein is an apparatus that includes: a first terminal configured to receive a serial write data signal that includes at least four bits transferred...
US-9,263,095 Memory having buried digit lines and methods of making the same
A memory array having memory cells and methods of forming the same. The memory array may have a buried digit line formed in a first horizontal planar volume, a...
US-9,262,425 Providing access to a collection via a plurality of discrete machine-recognizable codes
Systems and methods for providing access to a collection of related binary files via a collection of machine-recognizable codes provided on a device or consumer...
US-9,262,335 Re-building mapping information for memory devices
Memory modules and methods of operating memory modules re-build mapping information from data read from last valid physical pages. Corruption of mapping...
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