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Patent # Description
US-9,205,723 Dog shading screen
A removable dog screen for placement in the rear opening door of a vehicle to provide shade and ventilation to an animal within the vehicle for a short period...
US-9,204,703 Nail trimmer
A rear-pivot-point lever, cam-enabled, captured-spring-biased nail trimmer is disclosed. A base plate with a front cutting edge is pivotally connected to a top...
US-D745,157 Prosthetic device
US-D745,150 Vaginal manipulator
US-D745,148 Vaginal manipulator
US-9,204,487 Efficient operations of components in a wireless communications device
Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the...
US-9,203,898 Adaptive communication interface
Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and...
US-9,203,662 Multi-level signaling
Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits....
US-9,203,386 Analog delay lines and adaptive biasing
Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive...
US-9,203,025 Methods of forming repeating structures
Some embodiments include integrated memory having an array of repeating plates across a plurality of nodes. The array includes rows and columns. The plates...
US-9,202,871 JFET devices with increased barrier height and methods of making same
Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A...
US-9,202,860 Method for fabricating capacitor having rutile titanium oxide dielectric film
A method for fabricating a capacitor includes: (1) forming a bottom electrode on a substrate; (2) forming a template layer on the bottom electrode; (3)...
US-9,202,786 Low-resistance interconnects and methods of making same
Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present...
US-9,202,762 Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing
A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator...
US-9,202,714 Methods for forming semiconductor device packages
Methods for forming semiconductor device packages include applying an underfill material over a semiconductor wafer including conductive elements such that an...
US-9,202,700 Charge storage nodes with conductive nanodots
Methods of forming memory cells having conductive nanodots over a charge storage material are useful in non-volatile memory devices and electronic systems.
US-9,202,686 Electronic devices including barium strontium titanium oxide films
Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium...
US-9,202,595 Post package repair of memory devices
An apparatus for post package repair can include memory cells in a package. A storage element can store information responsive to a post-package repair mode...
US-9,202,586 Non-volatile memory programming
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line...
US-9,202,574 Memory device having a different source line coupled to each of a plurality of layers of memory cell arrays
In an embodiment, a memory device may have a plurality of layers of memory cell arrays. Each layer may have a plurality of strings of memory cells and a...
US-9,202,569 Methods for providing redundancy and apparatuses
Methods for providing redundancy and apparatuses are disclosed. One such method for providing redundancy performs a mapping of data between an address of a...
US-9,202,550 Appatuses and methods for precharge operations and accumulated charge dissipation
Examples described include precharge operations and circuitry for performing precharge operations. Digit lines may be driven to ground during a portion of...
US-9,202,542 Power supply induced signal jitter compensation
Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example...
US-9,202,333 Gaming device with a secure interface
A system for an electronic gambling device output has been developed. The system includes, a first computing device with gambling device game logic circuitry...
US-9,201,820 Solid state storage device controller with parallel operation mode
A master memory controller comprises a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with...
US-9,201,718 Data recovery in a solid state storage system
Methods for data recovery and memory systems are provided. According to at least one such method, when defective data is read from a memory location, the data...
US-9,201,705 Multi-partitioning of memories
Various embodiments comprise apparatuses and methods including a method of reconfiguring partitions in a memory device as directed by a host. The method...
US-9,201,489 Circuit, system and method for selectively turning off internal clock drivers
The present invention includes a circuit, system and method for selectively turning off internal clock drivers to reduce operating current. The present...
US-9,199,227 Methods of producing continuous boron carbide fibers
Methods of producing continuous boron carbide fibers. The method comprises reacting a continuous carbon fiber material and a boron oxide gas within a...
US-9,199,215 Compact Fischer Tropsch system with integrated primary and secondary bed temperature control
A Fischer Tropsch ("FT") reactor includes at least one FT tube. The FT tube may include a catalyst that is designed to catalyze an FT reaction, thereby creating...
US-9,198,779 Lever-actuated device for external prosthesis
A lever-actuated distal lock connects a limb liner to a prosthetic leg or arm hard socket. In some versions, air-sealing capability may limit/prevent air flow...
US-9,198,497 Hook for shoulder sling
Several versions of a holder for a shoulder sling or strap are described. Preferably, the holder may be secured to or manufactured in the shoulder strap of a...
US-D744,715 Safe
US-D744,374 Buckle bumper cover
US-9,197,251 Method and apparatus for reading data from non-volatile memory
Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes...
US-9,196,810 Vertical solid-state transducers having backside terminals and associated systems and methods
Vertical solid-state transducers ("SSTs") having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a...
US-9,196,753 Select devices including a semiconductive stack having a semiconductive material
Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first...
US-9,196,673 Methods of forming capacitors
A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support...
US-9,196,625 Self-aligned floating gate in a vertical memory structure
Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from...
US-9,196,619 Semiconductor device having metal bit line
Disclosed herein is a device that includes: a semiconductor substrate including a memory cell region and a peripheral circuit region arranged around the memory...
US-9,196,539 Method for separating and transferring IC chips
A method for separating a multiple number of semiconductor devices or semiconductor integrated circuits from a wafer on which the multiple number of...
US-9,196,530 Forming self-aligned conductive lines for resistive random access memories
Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of...
US-9,196,471 Scanner for wafers, method for using the scanner, and components of the scanner
A horizontal scanner, a vertical scanner, and a dual-configuration scanner that is able to convert between a horizontal scanner and a vertical scanner is...
US-9,196,370 Reducing noise in semiconductor devices
The present disclosure includes methods, devices, modules, and systems for reducing noise in semiconductor devices. One method embodiment includes applying a...
US-9,196,359 Read distribution management for phase change memory
Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.
US-9,196,357 Voltage stabilizing for a memory cell array
Voltage balancing for a memory cell array is provided. One example method of voltage balancing for a memory array can include activating an access node coupled...
US-9,196,355 Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a...
US-9,196,349 Semiconductor device
A device includes an output circuit, a DLL (Delay Locked Loop) circuit including a first delay line receiving a first clock signal and outputting, in response...
US-9,196,346 Non-volatile memory with LPDRAM
Memory, systems and devices are disclosed where a non-volatile memory device (such as a Flash memory device) is paired with a LPDRAM memory device or array and...
US-9,196,321 On-die termination apparatuses and methods
Apparatuses and methods are disclosed herein, including those, performed by a memory die, that operate to detect that a command on a bus connected to the memory...
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