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Patent # Description
US-9,259,982 Currency operated tire inflation and repair apparatus and methods
The present disclosure provides tire repair assemblies that can include: a tire sealant tank; an air assembly coupled to the tire sealant tank; a valve...
US-9,259,751 Dispensing container with enhanced appearance
A container comprising a body portion and a neck portion, the neck portion having a pump dispenser thereon, the pump dispenser comprising a pump mechanism, a...
US-9,259,683 Methods and apparatus for treating fluorinated greenhouse gases in gas streams
A method for removing fluorinated greenhouse gas from a gas stream comprises reacting at least one fluorinated greenhouse gas in a gas stream with at least one...
US-9,258,963 Pea variety SV7688QF
The invention provides seed and plants of the pea line designated SV7688QF. The invention thus relates to the plants, seeds and tissue cultures of pea line...
US-9,258,939 Hill-compensating planter and method
A seed planting device operable on ground includes a main frame, having wheels, configured to be moved in a planting direction on the ground, a seed hopper,...
US-9,258,536 Imaging systems with plasmonic color filters
An image sensor integrated circuit may contain image sensor pixels. A channel for receiving a fluid with particles such as fluorescent biological samples may be...
US-9,258,360 Intelligent disaster recovery for database connection failures
Embodiments of the invention provide techniques for disaster recovery in the event of a database connection failure. In one embodiment, a network address for a...
US-9,257,995 Apparatuses and methods for mitigating uneven circuit degradation of delay circuits
Apparatuses and methods for mitigating uneven circuit degradation of delay circuits are disclosed. In an example method, an imbalance in transistor threshold...
US-9,257,648 Memory cells, methods of forming memory cells, and methods of programming memory cells
Some embodiments include methods in which a memory cell is formed to have programmable material between first and second access lines, with the programmable...
US-9,257,646 Methods of forming memory cells having regions containing one or both of carbon and boron
Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate...
US-9,257,431 Memory cell with independently-sized electrode
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle...
US-9,257,430 Semiconductor construction forming methods
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a...
US-9,257,294 Methods and apparatuses for energetic neutral flux generation for processing a substrate
Apparatuses and methods for processing substrates are disclosed. A processing apparatus includes a chamber for generating a plasma therein, an electrode...
US-9,257,256 Templates including self-assembled block copolymer films
Methods for fabricating sublithographic, nanoscale microstructures arrays including openings and linear microchannels utilizing self-assembling block...
US-9,257,203 Setting a default read signal based on error correction
Apparatuses and methods related to setting a default read signal based on error correction include reading a page of data from a group of memory cells with a...
US-9,257,197 Apparatuses and/or methods for operating a memory cell as an anti-fuse
Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
US-9,257,182 Memory devices and their operation having trim registers associated with access operation commands
Methods, and apparatus configured to perform methods, including loading trim settings into a trim register of a memory device associated with a command for an...
US-9,257,180 Random telegraph signal noise reduction scheme for semiconductor memories
Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal...
US-9,257,155 Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or...
A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i)...
US-9,257,154 Methods and apparatuses for compensating for source voltage
Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write...
US-9,257,136 Magnetic tunnel junctions
A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is...
US-9,256,577 Apparatuses and related methods for overflow detection and clamping with parallel operand processing
A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The disclosure predicts...
US-9,256,134 Photoresist removal
Disclosed herein is a composition and method for semiconductor processing. In one embodiment, a wet-cleaning composition for removal of photoresist is provided....
US-9,255,964 Electronic apparatus having IC temperature control
The use of a power sink function in IC testing results in a simple and rapid method for testing ICs, and assembled modules, at elevated temperature profiles...
US-9,255,023 Treatment of contaminated impound water
Systems and methods for treating contaminated impound water are disclosed which include a pretreatment stage wherein contaminated water is oxidized, pH...
US-9,254,792 Equipment storage and retrieval system
An equipment storage and retrieval system retrieves equipment from the back of pick-up trucks and other cargo carrying vehicles. A guide rail and a frame with...
US-9,254,448 Sublimation systems and associated methods
A system for vaporizing and sublimating a slurry comprising a fluid including solid particles therein. The system includes a first heat exchanger configured to...
US-9,254,417 Sprint trainer aid
Disclosed is a sprinter training aid which pulls the sprinter forward in an over speed condition, for the purpose of exercise the muscles which pull the leg...
US-9,252,996 Apparatuses and methods to change information values
Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the...
US-9,252,709 Apparatuses and methods for providing oscillation signals
Apparatuses and methods are disclosed for oscillators that are substantially insensitive to supply voltage variations. In one such example apparatus, a...
US-9,252,362 Method for making three dimensional memory array architecture using phase change and ovonic switching materials
Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality...
US-9,252,281 Silicon on germanium
A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film...
US-9,252,188 Methods of forming memory cells
Some embodiments include methods of forming memory cells. A series of rails is formed to include bottom electrode contact material. Sacrificial material is...
US-9,252,176 Ambient infrared detection in solid state sensors
A solid state imaging device includes an array of active pixels and an infrared cut filter formed over the sensor. Optionally, a slot in the infrared cut filter...
US-9,252,148 Methods and apparatuses with vertical strings of memory cells and support circuitry
Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed...
US-9,252,119 Ball grid array including redistribution layer, packaged integrated circuit including the same, and methods of...
Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA...
US-9,251,908 Memory kink checking
This disclosure concerns memory kink checking. One embodiment includes selectively applying one of a plurality of voltages to a first data line according to a...
US-9,251,907 Memory devices and methods of operating memory devices including applying a potential to a source and a select...
Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first...
US-9,251,897 Methods for a phase-change memory array
Methods of operating phase-change memory arrays are described. A method includes determining a pattern to be written to a phase-change memory array and...
US-9,251,895 Immunity of phase change material to disturb in the amorphous phase
Disturb from the reset to the set state may be reduced by creating an amorphous phase that is substantially free of crystal nuclei when programming the reset...
US-9,251,867 Voltage generators having reduced or eliminated cross current
Embodiments described include voltage generators having reduced or eliminated cross current. Dynamic adjustment of a low or high threshold voltage used in a...
US-9,251,860 Memory devices with local and global devices at substantially the same level above stacked tiers of memory...
In an embodiment, a memory device includes a stack of tiers of memory cells, a tier of local devices at a level above the stack of tiers of memory cells, and a...
US-9,251,068 Systems, devices, memory controllers, and methods for memory initialization
Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel....
US-9,251,065 Execute-in-place mode configuration for serial non-volatile memory
Example embodiments for configuring a serial non-volatile memory device for an execute-in-place mode may comprise a non-volatile configuration register to store...
US-9,251,000 Apparatuses and methods for combining error coding and modulation schemes
Methods and apparatuses for combining error coding and modulation schemes are described herein. One or more methods include encoding data using linear error...
US-9,250,745 Determine the characteristics of an input relative to a projected image
Embodiments disclosed herein relate to an input relative to an image projected onto a projection surface. In one embodiment, a processor may determine the...
US-9,249,498 Forming memory using high power impulse magnetron sputtering
Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on...
US-9,247,234 Imagers with depth sensing capabilities
An imager may include depth sensing pixels that provide an asymmetrical angular response to incident light. The depth sensing pixels may each include a...
US-9,247,170 Triple conversion gain image sensor pixels
An image sensor having pixel circuitry operable in multiple gain modes is provided. The pixel circuitry may include first and second floating diffusion (FD)...
US-9,246,746 Reliable systems and methods for network notifications
The present disclosure provides reliable systems and methods for network notifications, i.e. Simple Network Management Protocol version 2 Protocol Data Unit...
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