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Patent # Description
US-9,099,457 Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor...
US-9,099,442 Conductive interconnect structures incorporating negative thermal expansion materials and associated systems,...
Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device...
US-9,099,431 Polishing systems and methods for removing conductive material from microelectronic substrates
Polishing systems and methods for removing conductive material (e.g., noble metals) from microelectronic substrates are disclosed herein. Several embodiments of...
US-9,099,402 Integrated circuit structure having arrays of small, closely spaced features
Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can...
US-9,099,314 Pitch multiplication spacers and methods of forming the same
Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of...
US-9,099,309 Method providing an epitaxial growth having a reduction in defects and resulting structure
Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size...
US-9,099,272 Field emission devices and methods for making the same
The present disclosure includes field emission device embodiments. The present disclosure also includes method embodiments for forming field emitting devices....
US-9,099,189 Methods and devices for memory reads with precharged data lines
Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair...
US-9,099,182 Method and apparatus for selective use of wear-leveling to store data in a memory
Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash...
US-9,099,174 Drift acceleration in resistance variable memory
The present disclosure includes apparatuses and methods including drift acceleration in resistance variable memory. A number of embodiments include applying a...
US-9,098,440 Secure compact flash
Methods and apparatus are provided, such as a memory card with a processor and nonvolatile memory coupled thereto. The nonvolatile memory has a secure area...
US-9,097,289 Friction plate design for multi-plate wet friction clutch
An improved friction plate is disclosed. The friction plate incorporates friction pads having substantially V Shaped Grooves having an angle offset to the axis...
US-9,096,730 Methods of utilizing block copolymer to form patterns
Some embodiments include methods of forming patterns. A block copolymer film may be formed over a substrate, with the block copolymer having an intrinsic glass...
US-9,096,340 Box design with corner stack tabs
The present disclosure relates to improved box designs and methods of making stackable boxes having improved designs. Some embodiments include boxes having...
US-9,095,438 Surgical implant for ostectomy procedures
In one instance, the disclosure is a moldable, biocompatible, bioactive, and resorbable hip implant made to be implanted after femoral head ostectomy. The hip...
US-D735,558 Fence T-post bracket pair
US-9,094,621 Document management
A document management method is disclosed. The method includes generating and merging a unique watermark for and with each page of a print job to be produced....
US-9,094,280 Communicating network status
A method for communicating network status information includes receiving, via a first link, a request for status information from a client device, the first...
US-9,093,641 Methods of forming memory cells, and methods of patterning chalcogenide-containing stacks
Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed...
US-9,093,636 Incorporation of oxygen into memory cells
Electronic apparatus, systems, and methods include a resistive random access memory cell having an oxygen gradient in a variable resistive region of the...
US-9,093,589 Solid state lighting devices without converter materials and associated methods of manufacturing
Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a...
US-9,093,579 Dielectric barriers for pixel arrays
Pixel arrays are provided for image sensors that have barriers between color filters in an array of color filters. Color filter barriers may be formed from a...
US-9,093,368 Nonvolatile memory cells and arrays of nonvolatile memory cells
A nonvolatile memory cell includes first and second electrodes. Programmable material and a select device are received in series between and with the first and...
US-9,093,367 Methods of forming doped regions in semiconductor substrates
Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first...
US-9,093,311 Techniques for providing a semiconductor memory device
Techniques for providing a semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a semiconductor memory device...
US-9,093,266 Forming high aspect ratio isolation structures
An isolation structure, such as a trench isolation structure, may be formed by forming an aperture in a semiconductor substrate and then filling the aperture...
US-9,093,162 Sensing memory cells
The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to...
US-9,093,152 Multiple data line memory and methods
Apparatuses and methods are disclosed, including an apparatus with rows of vertical strings of memory cells coupled to a common source and multiple data lines...
US-9,093,147 Method and apparatus for common source line charge transfer
A method and apparatus for charge transfer comprising a resistive random access memory (ReRAM) cell, coupled to a common source voltage line (CSL) for...
US-9,093,142 Phase change memory adaptive programming including pulse transition time adjustment
Some embodiments include methods and apparatus having a module configured to program a memory cell using a signal to cause the memory cell to have a programmed...
US-9,092,388 Bus width negotiation
There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad...
US-9,092,387 Non-volatile memory device capable of initiating transactions
A non-volatile memory may operate, not in a master/slave arrangement, but in a peer-to-peer arrangement. In some embodiments, the memory may initiate a...
US-9,091,705 System and method for high-speed atomic force microscopy with switching between two feedback loops
A high-speed atomic force microscope (HSAFM) is disclosed herein. The HSAFM includes a cantilever, a piezotube, an optical detector, a circuit element, and a...
US-9,091,251 Actuation method and apparatus, micropump, and PCR enhancement method
An actuation apparatus includes at least one magnetic shape memory (MSM) element containing a material configured to expand and/or contract in response to...
US-9,090,460 Plasma processing with preionized and predissociated tuning gases and associated systems and methods
Plasma processing systems and methods for using pre-dissociated and/or pre-ionized tuning gases are disclosed herein. In one embodiment, a plasma processing...
US-9,089,987 Rotary knife fixture for cutting spiral, textured potato pieces
A rotary knife fixture for cutting vegetable products such as raw potatoes into spiral shapes. The knife fixture includes a ring-shaped blade holder driven...
US-9,089,365 Tissue fixation device
Tissue fixation members interact with a housing to hold tissue relative to the housing and allow the orientation and position of the grasped tissue to be...
US-D735,294 Filter for liquid
US-RE45,633 Reduced crosstalk sensor and method of formation
Isolation methods and devices for isolating regions of a semiconductor device are disclosed. The isolation methods and structures include forming an isolating...
US-9,088,907 Node fault identification in wireless LAN access points
A wireless access point array having a plurality of access point radios, a monitor radio and an array controller. The array controller includes processes,...
US-9,088,418 System and method for updating read-only memory in smart card memory modules
A storage device contains a smart-card device and a memory device, both connected to a controller. The storage device may be used in the same manner as a...
US-9,088,303 Codewords that span pages of memory
The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a...
US-9,087,989 GCIB-treated resistive device
The present disclosure includes GCIB-treated resistive devices, devices utilizing GCIB-treated resistive devices (e.g., as switches, memory cells), and methods...
US-9,087,895 Vertical devices and methods of forming
Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor...
US-9,087,874 Methods of forming graphene-containing switches
Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive...
US-9,087,737 Methods of forming charge storage structures including etching diffused regions to form recesses
Methods are disclosed that include selectively etching diffused regions to form recesses in semiconductor material, and forming charge storage structures in the...
US-9,087,730 DRAM with nanofin transistors
One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second...
US-9,087,721 Devices including fin transistors robust to gate shorts and methods of making the same
Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench in a substrate, substantially or entirely...
US-9,087,699 Methods of forming an array of openings in a substrate, and related methods of forming a semiconductor device...
A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a...
US-9,087,604 Pre-charging method applied in dynamic random access memories
A pre-charging method applied in DRAM which includes steps of: enabling wordlines in an active array and an reference array; disabling the wordlines in the...
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