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Patent # Description
US-9,161,026 Systems and methods for calibrating an imager
One example discloses a method for calibrating an imager. A plurality of images of a target, each having an associated integration time, are captured at the...
US-9,160,561 High speed ring/bus
A data communication bus and method of operation thereof, including a plurality of nodes connected to a respective plurality of media segments. A typical node...
US-9,160,349 Die location compensation
Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function...
US-9,159,921 Resistive memory cell
Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method...
US-9,159,913 Two-terminal reversibly switchable memory device
A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen...
US-9,159,896 Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
US-9,159,845 Charge-retaining transistor, array of memory cells, and methods of forming a charge-retaining transistor
A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes...
US-9,159,829 Recessed transistors containing ferroelectric material
Some embodiments include transistor constructions having a first insulative structure lining a recess within a base. A first conductive structure lines an...
US-9,159,780 Methods of forming capacitors
A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the...
US-9,159,736 Data line arrangement and pillar arrangement in apparatuses
Some embodiments include an apparatus having semiconductor pillars in a substantially hexagonally closest packed arrangement. The hexagonally closest packed...
US-9,159,731 Methods of forming capacitors and semiconductor devices including a rutile titanium dioxide material
Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium...
US-9,159,677 Methods of forming semiconductor device structures
A method of forming a semiconductor device structure comprises forming at least one reflective structure comprising at least two dielectric materials having...
US-9,159,662 Semiconductor structures having adhesion promoting layer in cavities
High aspect ratio trenches may be filled with metal that grows more from the bottom than the top of the trench. As a result, the tendency to form seams or to...
US-9,159,569 Methods of forming charge-trapping regions
Some embodiments include methods of forming charge-trapping zones. The methods may include forming nanoparticles, transferring the nanoparticles to a liquid to...
US-9,159,551 Methods of forming capacitors
A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner...
US-9,159,452 Automatic word line leakage measurement circuitry
The present invention is a circuit and method for measuring leakage on the plurality of word lines in a memory device. In one embodiment, a memory device may...
US-9,159,408 Memory element with a reactive metal layer
A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive...
US-9,159,397 Methods and apparatuses for refreshing memory
Apparatuses and methods for memory refreshing memory cells is described. An example method includes receiving a self refresh command at a memory. The method...
US-9,159,393 Memory decoding
Memories, and methods of operating such memories, having a memory cell, sense circuitry having a gate, program circuitry and a decoder having a first signal...
US-9,159,392 Memory device word line drivers and methods
Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at...
US-9,159,383 Signal management in a memory device
Command signal management methods and circuits in memory devices are disclosed. Command signals are selectively passed and blocked to enforce safe operating...
US-9,159,375 Selectively conducting devices, diode constructions, methods of forming diodes and methods of current modulation
Some embodiments include selectively conducting devices having a first electrode, a second electrode, and dielectric material between the first and second...
US-9,159,373 Enhanced block copy
Methods and apparatuses for an enhanced block copy. One embodiment is reading data from a source block located in a first portion of the memory device, and...
US-9,159,008 Method and apparatus for estimating usage of print substance in a printer
Embodiments of the present disclosure provide a method for estimating usage of a print substance. The method comprises receiving a plurality of pixels of a page...
US-9,159,005 Method and apparatus for optimizing memory usage in an imaging device
A system including a communication interface, a memory, and a processor. The communication interface is configured to receive data. The memory is divided into a...
US-9,158,709 Power cycling event counters for invoking security action
Subject matter disclosed herein relates to memory devices and security of same.
US-9,158,667 Apparatuses and methods for performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an...
US-9,158,634 Error control coding
A data writer is described comprising: a memory to store at least one amount of source data that is to be written to a data storage medium; a processor to...
US-9,158,612 Refresh of non-volatile memory cells based on fatigue conditions
In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment,...
US-9,158,607 Apparatuses and methods for operating a memory device
Subject matter described pertains to apparatuses and methods for operating a memory device.
US-9,158,336 Cases for tablet computers and methods
Cases for tablet computers and methods are disclosed. An embodiment of one such case has an interface configured to allow the tablet computer to communicate...
US-9,157,960 Through-substrate via (TSV) testing
Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments,...
US-9,157,565 Encapsulated insulation
This application describes insulated casings with cores of insulating material, coated with or otherwise encapsulated in a shell material are disclosed. A hinge...
US-9,157,489 External adjuster for clutch incorporating an expanding friction disk
An adjuster is disclosed, to be placed "in-line" to a clutch disengagement system. The adjuster provides a means for lifting the pressure plate above the clutch...
US-9,157,014 Adhesives including a filler material and related methods
Temporary adhesives include a thermoplastic polymer comprising from about 30% by weight to about 80% by weight of the temporary adhesive, a solvent comprising...
US-9,156,660 Lifting bale
What is disclosed is a lifting bale that has at least two side supports, at least two cross support, and at least one center support and ideally configured to...
US-9,154,459 Access control manager
A network access manager controls access to a network interface according to a set of access control instructions specifying permissible and impermissible...
US-9,154,141 Continuous high-frequency event filter
A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is...
US-9,154,131 Enhanced performance memory systems and methods
Digital memory devices and systems, including memory systems and methods for operating such memory systems are disclosed. In the embodiments, a memory system...
US-9,153,890 Singulated elastomer electrical contactor for high performance interconnect systems and method for the same
A method and an electrical interconnect mechanism in which elastomeric pins are printed onto metal retainer tabs having at least one protrusion or tab extending...
US-9,153,777 Thermally optimized phase change memory cells and methods of fabricating the same
A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode...
US-9,153,776 Memory cells and methods of forming memory cells
Some embodiments include a memory cell having an electrode and a switching material over the electrode. The electrode is a first composition which includes a...
US-9,153,758 Method of attaching a light emitting device to a support substrate
A method according to embodiments of the invention includes providing a wafer of semiconductor light emitting devices, each semiconductor light emitting device...
US-9,153,614 Method and apparatus for lens alignment for optically sensitive devices and systems implementing same
Non-symmetrically located lenses are employed with semiconductor devices comprising optically active regions which are non-symmetrically located on a surface...
US-9,153,526 Microelectronic devices and methods for manufacturing microelectronic devices
Microelectronic devices and methods for manufacturing microelectronic devices are disclosed herein. One such method includes forming a plurality of apertures in...
US-9,153,520 Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods
Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die...
US-9,153,497 Semiconductor constructions
Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces....
US-9,153,491 Methods for forming conductive elements and vias on substrates and for forming multi-chip modules
Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a...
US-9,153,485 Methods of processing substrates and methods of forming conductive connections to substrates
Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method...
US-9,153,458 Methods of forming a pattern on a substrate
A method of forming a pattern on a substrate includes forming a repeating pattern of four first lines elevationally over an underlying substrate. A repeating...
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