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Patent # Description
US-8,964,448 Memory cells having a plurality of resistance variable materials
Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an...
US-8,964,245 Color plane registration error measurement
A color plane registration error method and system include printing a plurality of predetermined patterns of dots, each predetermined pattern having the...
US-8,963,719 Systems and methods to selectively connect antennas to receive and backscatter radio frequency signals
Systems and methods to selectively attach and control antennas via diodes and current sources. In one embodiment, a system includes: an RFID reader having a...
US-8,963,646 Delay line ring oscillation apparatus
The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer...
US-8,963,604 Methods, apparatuses, and circuits for bimodal disable circuits
Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter...
US-8,963,532 Reference current distribution
Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense...
US-8,963,438 Self-identifying solid-state transducer modules and associated systems and methods
Self-identifying solid-state transducer (SST) modules and associated systems and methods are disclosed herein. In several embodiments, for example, an SST...
US-8,963,331 Semiconductor constructions, semiconductor processing methods, methods of forming contact pads, and methods of...
Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which...
US-8,963,330 Circuit structures and electronic systems
The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating...
US-8,963,302 Stacked packaged integrated circuit devices, and methods of making same
A device is disclosed which includes a first packaged integrated circuit device, a second packaged integrated circuit device positioned above the first packaged...
US-8,963,292 Semiconductor device having backside redistribution layers and method for fabricating the same
Present embodiments relate to a semiconductor device having a backside redistribution layer and a method for forming such a layer. Specifically, one embodiment...
US-8,963,279 Semiconductor device isolation structures
Structures and methods are disclosed for the electrical isolation of semiconductor devices. A method of forming a semiconductor device may include providing a...
US-8,963,220 Shallow trench isolation for a memory
In some embodiments, a gate structure with a spacer on its side may be used as a mask o form self-aligned trenches in microelectronic memory, such as a flash...
US-8,963,156 Semiconductor devices including WiSX
Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon...
US-8,963,121 Vertical solid-state transducers and high voltage solid-state transducers having buried contacts and associated...
Solid-state transducers ("SSTs") and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular...
US-8,963,024 Sensor pass through assembly
Contemplated device, assembly and methods include a sensor feed through assembly that protects and seals a set of wires. The assembly has a body, a first seal,...
US-8,963,015 Capacitor coupled cable shield feedthrough
Shielding performance and protection from radiated RF energy at a cable's point of entry to an enclosure are improved when a shield of the cable is AC coupled...
US-8,962,926 Pea line EX 08570957
The invention provides seed and plants of the pea line designated EX 08570957. The invention thus relates to the plants, seeds and tissue cultures of pea line...
US-8,962,482 Multi-layer interconnect with isolation layer
An integrated circuit interconnect is fabricated by using a mask to form a via in an insulating layer for a conductive plug. After the plug is formed in the...
US-8,962,465 Methods of forming gated devices
Some embodiments include methods of forming gated devices. An upper region of a semiconductor material is patterned into a plurality of walls that extend...
US-8,962,460 Methods of selectively forming metal-doped chalcogenide materials, methods of selectively doping chalcogenide...
Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating...
US-8,962,449 Methods for processing semiconductor devices
Methods of forming a semiconductor structure include exposing a carrier substrate to a silane material to form a coating, removing a portion of the coating at...
US-8,962,447 Bonded strained semiconductor with a desired surface orientation and conductance direction
According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to...
US-8,962,446 Methods of forming oxides, methods of forming semiconductor constructions, and methods of forming isolation regions
Some embodiments include methods of forming isolation regions in which spin-on material (for example, polysilazane) is converted to a silicon dioxide-containing...
US-8,962,445 Method of manufacture of semiconductor isolation structure
A method of formation of an isolation structure for vertical semiconductor devices, the resulting isolation structure, and a memory device to prevent leakage...
US-8,962,431 Methods of forming metal silicide-comprising material and methods of forming metal silicide-comprising contacts
A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over...
US-8,962,401 Double gated 4F2 dram CHC cell and methods of fabricating the same
A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein...
US-8,962,387 Methods of forming memory cells
Some embodiments include methods of forming memory cells in which a metal oxide material is formed over a first electrode material, an oxygen-sink material is...
US-8,962,384 Memory cells having heaters with angled sidewalls
Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive...
US-8,960,590 Pressure-equalizing cradle for booster rocket mounting
A launch system and method improve the launch efficiency of a booster rocket and payload. A launch aircraft atop which the booster rocket is mounted in a...
US-8,959,759 Method for assembling computer modules small in thickness
Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module...
US-D722,822 Cutter blade
US-8,959,387 Tape drive retry
The present disclosure provides techniques for operating a tape drive. A method of operating a tape drive includes monitoring a parameter of the tape drive...
US-8,959,326 Memory device initiate and terminate boot commands
Methods of operating memory devices and electronic systems having memory devices include initiating a boot mode of operation of the memory device in response to...
US-8,959,295 Bit inversion in memory devices
Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the...
US-8,958,636 Configurable color trapping
Embodiments of the present disclosure provide a method of color trapping to improve perceived image quality. The color trapping may be subject to one or more...
US-8,958,261 Low power protection circuit
The present invention provides the low power protection circuit including a first voltage detector, a pulse generating circuit, a SR latch, and an output logic...
US-8,958,260 Systems and methods for voltage sensing and reporting
Semiconductor devices comprising at least one voltage sensor for sensing an operating voltage associated with an operational circuit of the semiconductor...
US-8,958,256 Apparatuses and methods for improved memory operation times
Apparatuses and methods for improved memory cycle times are disclosed. An example apparatus may include first and second lines and a sense amplifier. The sense...
US-8,958,242 Thermal treatment of flash memories
A memory controller can provide current to a heater in a flash memory to reduce cycling induced errors. If necessary, after heating, the memory may be...
US-8,958,233 Stabilization of resistive memory
The present disclosure includes apparatuses and methods including stabilization of resistive memory. A number of embodiments include applying a programming...
US-8,957,495 Memory cell profiles
Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from...
US-8,957,483 Electrically conductive lines and integrated circuitry comprising a line of recessed access devices
A method of forming an electrically conductive buried line and an electrical contact thereto includes forming of a longitudinally elongated conductive line...
US-8,957,403 Select devices including an open volume, and related methods, memory devices, and electronic systems
Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a...
US-8,956,981 Methods of eliminating pattern collapse on photoresist patterns
A stabilizing solution for treating photoresist patterns and methods of preventing profile abnormalities, toppling and resist footing are disclosed. The...
US-8,956,976 Methods of processing semiconductor substrates in forming scribe line alignment marks
A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe...
US-8,956,974 Devices, systems, and methods related to planarizing semiconductor devices after forming openings
Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stop layer and...
US-8,956,713 Methods of forming a stamp and a stamp
A method of patterning a substrate is disclosed. An ink material is chemisorbed to at least one region of a stamp and the chemisorbed ink material is...
US-8,956,498 Apparatuses facilitating fluid flow into via holes, vents, and other openings communicating with surfaces of...
A method for removing material from surfaces of at least a portion of at least one recess or at least one aperture extending into a surface of a substrate...
US-8,955,894 Adjustable spreader bar system
In the crane industry, there is a need to efficiently attach, move, and unattach loads to crane hooks. When the load has an asymmetrical center of gravity, two...
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