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Patent # Description
US-1,006,1643 Estimating an error rate associated with memory
The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored...
US-1,006,1590 Generating and executing a control flow
The present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device...
US-1,006,1541 Systems and methods for refreshing a memory bank while accessing another memory bank using a shared address path
A system includes multiple memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the...
US-1,006,0703 Apparatus and method for calculating aiming point information
The present invention relates to target acquisition and related devices, and more particularly to telescopic gunsights and associated equipment used to achieve...
US-1,005,9144 Remote acting articulating tool holder
An articulated tool holder on an extension pole. The device uses an extension pole with a pivoting tool holder on the end of the pole. The tool holder is...
US-D827,061 Sliding exercise apparatus
US-1,005,7313 System to dynamically adjust request values at a back-end application server
According to some embodiments, systems, methods, apparatus, computer program code and means may receive data streams from remote third-party administrator...
US-1,005,6428 Semiconductor device and method of forming curved image sensor region robust against buckling
A semiconductor wafer has a plurality of non-rectangular semiconductor die with an image sensor region. The non-rectangular semiconductor die has a circular,...
US-1,005,6386 Memory cells and memory arrays
Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first...
US-1,005,6359 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated...
Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked...
US-1,005,6338 Methods of forming semiconductor packages including molding semiconductor chips of the semiconductor packages
Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor...
US-1,005,6157 Memory apparatus with post package repair
Apparatuses for memory repair for a memory device are described. An example apparatus includes: a non-volatile storage element that stores information; a...
US-1,005,6154 Apparatuses and methods for flexible fuse transmission
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each...
US-1,005,6149 Semiconductor memory column decoder device and method
Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in...
US-1,005,6137 Apparatuses and methods for accessing memory cells
Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to...
US-1,005,6129 Cell bottom node reset in a memory array
Methods, systems, and devices for cell bottom node reset in a memory array are described. The memory array may include a plurality of ferroelectric memory cells...
US-1,005,6122 Apparatuses and methods for performing compare operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can...
US-1,005,6120 Interconnection for memory electrodes
Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central...
US-1,005,5293 High performance memory controller
A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an...
US-1,005,5285 Physical page, logical page, and codeword correspondence
The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a...
US-1,005,5196 Division operations for memory
Examples of the present disclosure provide apparatuses and methods for performing division operations in a memory. An example apparatus comprises a first...
US-1,005,3887 Protective barriers and related methods
Protective barriers for protecting assets (e.g., electrical power transformers and other substation components). The protective barrier may include a lower...
US-1,005,3209 Aircraft winglet design having a compound curve profile
An improved winglet design is presented for aircraft wherein the winglet configuration is well suited for aircraft wings having moderate to no aft swept, or...
US-1,005,3105 Drive mode selection for an autonomous vehicle
A method for controlling an off-road vehicle includes selecting an operating mode from a plurality of candidate operating modes. The plurality of candidate...
US-1,005,2663 Food article defect removal apparatus
A food article defect removal apparatus includes a manifold that defines one or more chambers for holding pressurized fluid. First channels extend from a first...
US-1,005,1936 Item and luggage loss prevention system
Novel tools and techniques are provided for implementing item or luggage loss prevention, which, in some cases, is based on weight measurement. In some...
US-1,005,1873 Processes for removal of lactose from dried milk products
Disclosed are processes for removing lactose from dried milk products to produce dried protein fortified and/or mineral fortified milk products having a reduced...
US-1,005,0832 Server clustering in mobile computing environment
A clustered server system and a method for maintaining a server cluster involve a plurality of servers that collectively form a server cluster. A master...
US-1,005,0180 LED with stress-buffer layer under metallization layer
Semiconductor LED layers are epitaxially grown on a patterned surface of a sapphire substrate. The patterned surface improves light extraction. The LED layers...
US-1,005,0085 Block architecture for vertical memory array
Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area...
US-1,005,0084 Replacement materials processes for forming cross point memory
Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line...
US-1,005,0049 Apparatuses including memory arrays with source contacts adjacent edges of sources
Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device...
US-1,005,0023 Solid state lighting device with different illumination parameters at different regions of an emitter array
Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a...
US-1,004,9874 Self-assembled nanostructures including metal oxides and semiconductor structures comprised thereof
A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an...
US-1,004,9756 Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data...
A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source. The...
US-1,004,9750 Methods including establishing a negative body potential in a memory cell
Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation...
US-1,004,9737 Memory cell architecture for multilevel cell programming
Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary...
US-1,004,9722 Apparatuses and methods for a memory device with dual common data I/O lines
Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O...
US-1,004,9721 Apparatuses and methods for in-memory operations
The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of...
US-1,004,9713 Full bias sensing in a memory array
Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be...
US-1,004,9707 Shifting data
The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus...
US-1,004,9705 Memories having select devices between access lines and in memory cells formed of a same type of circuit element
Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of...
US-1,004,9443 Method and system for determining the presence or absence of a part of an assembly within a work cell
A method and system for determining the presence or absence of a part of an assembly within at least one user-defined, 3-D detection region within a work cell...
US-1,004,9207 Methods of operating storage systems including encrypting a key salt
A method of operating a storage system includes using the device driver to combine a password, the key salt, and the number of iterations to generate a primary...
US-1,004,9054 Virtual register file
The present disclosure is related to a virtual register file. Source code can be compiled to include references to a virtual register file for data subject to a...
US-1,004,9038 Memory devices with register banks storing actuators that cause operations to be performed on a memory core
A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic...
US-1,004,8888 Apparatuses and methods for partitioned parallel data movement
The present disclosure includes apparatuses and methods for partitioned parallel data movement. An example apparatus includes a memory device that includes a...
US-1,004,8887 Apparatuses and methods for single level cell caching
Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of...
US-1,004,8882 Non-volatile memory with LPDRAM
Low power DRAM (LPDRAM) memory devices for communication with a non-volatile memory coupled to the LPDRAM memory device, and systems containing such LPDRAM and...
US-1,004,7625 Fan blade root integrated sealing solution
A gas turbine engine, a fan section for a gas turbine engine, and a method for assembling a fan section of a gas turbine engine are disclosed. The fan section...
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